hoangt Goto Github PK

pycoram

Python-based Portable IP-core Synthesis Framework for FPGA-based Computing

pydgin

A (Py)thon (D)SL for (G)enerating (In)struction set simulators.

pymoschar

pyncs

pyNCS is a python library that allows easy access to Neuromorphic Chips and Systems (NCS),

pynn

A Python package for simulator-independent specification of neuronal network models.

pynq

Python Productivity for ZYNQ

pyrtl

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.

pyverilog

Python-based Verilog Parser (currently Netlist only)

pyverilog-1

Python-based Hardware Design Processing Toolkit for Verilog HDL

q2m-sim

A tool that uses QSim to generate x86 instruction traces that can be fed to MacSim

qflex

Quick & Flexible Computer Architecture Simulation.

qnetsim

Network Simulator for Surface Code Quantum Computation

qnn-mo-pynq

qnnpack

Quantized Neural Network PACKage - mobile-optimized implementation of quantized neural network operators

qsim

QEMU based emulation library for micro-architectural simulation (ARM64 and x86)

quadcoptersystem

The hardware and software for our quadcopter system

quantlib

The QuantLib C++ library

quantumsim

Quantumsim, a GPU-accellerated full density matrix simulator of quantum circuits

quartz

Quartz: A DRAM-based performance emulator for NVM

r-vex

A reconfigurable and extensible VLIW processor implemented in VHDL

rabbits

ramulator

A Fast and Extensible DRAM Simulator. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

rapl-tools

Tools for monitoring CPU power with Intel's RAPL interface

rapl_power_meter

This utility implements a software power meter using RAPL

rapl_validation

Results from RAPL DRAM validation tests

raplread

raplread is a library to read and print power and energy statistics from Intel's RAPL (Running Average Power Limit) interface

rc-fpga-zcu

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

redeye_sim

RedEye is a vision sensor designed to execute early stages of a deep convolutional neural network (ConvNet) in the analog domain. This repo is a modification of Caffe to train, simulate and visualize analog ConvNet processing under noise vs. energy tradeoffs.

reflex

ReFlex: Remote Flash == Local Flash

reloc

Designing Relocatable FPGA Partitions with Vivado Design Suite