Topic: axi4 Goto Github
Some thing interesting about axi4
Some thing interesting about axi4
axi4,RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
User: aignacio
axi4,An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
Organization: airhdl
axi4,A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
User: amamory
axi4,AXI stream protocol checking design
User: amamory
axi4,A demonstrator of Hermes network-on-chip communicating with the ARM processor
User: amamory
axi4,Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface
User: amamory
axi4,RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
User: ammar-bin-amir
axi4,VeeR EH1 core
Organization: chipsalliance
axi4,VeeR EL2 Core
Organization: chipsalliance
Home Page: https://chipsalliance.github.io/Cores-VeeR-EL2/html/index.html
axi4,Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
User: cspyridakis
axi4,An AXI4 crossbar implementation in SystemVerilog
User: dpretet
axi4,Functional Bus Description Language compiler front-end written in Go.
Organization: functional-bus-description-language
axi4,Open-Source AXI4 DMA Engine in SystemVerilog and Chisel
User: gednyengs
axi4,Synchronous and Asynchronous FIFO with AXI interface
User: gururavi
Home Page: https://github.com/gururavi/rtl
axi4,这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS
User: hanley-yao
axi4,HLS for Networks-on-Chip
Organization: ic-lab-duth
axi4,Quasar 2.0: Chisel equivalent of SweRV-EL2
Organization: lampro-mellon
axi4,《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
User: loykylewong
axi4,AXI4 and AXI4-Lite interface definitions
User: mmxsrup
axi4,Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.
User: mnemocron
axi4,AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
Organization: osvvm
axi4,AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Organization: pulp-platform
axi4,Common SystemVerilog RTL modules for RgGen
Organization: rggen
Home Page: https://github.com/rggen/rggen
axi4,Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
Organization: rismicrodevices
axi4,A collection of formal properties for hardware buses, and cores using them.
User: rlee287
axi4,A group of typed definition of AXI4 in Chisel3.
Organization: shanghaitechgeekpie
axi4,Network on Chip Implementation written in SytemVerilog
User: taichi-ishitani
axi4,AMBA AXI VIP
User: taichi-ishitani
axi4,Minimal DVI / HDMI Framebuffer
User: ultraembedded
axi4,FTDI FT600 SuperSpeed USB3.0 to AXI bus master
User: ultraembedded
axi4,FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
User: ultraembedded
axi4,SDRAM controller with AXI4 interface
User: ultraembedded
axi4,SPI-Flash XIP Interface (Verilog)
User: ultraembedded
axi4,Cortex-M0 DesignStart Wrapper
User: ultraembedded
axi4,An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-DDR-SDRAM
axi4,[Course] Hands-On ZYNQ: Mastering AXI4 Bus Protocol
User: yohanes-erwin
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