chipsalliance/cores-veer-eh1

VeeR EH1 core

cores-veer-eh1's Issues

Boot code from iccm

Hi , if we want to use the iccm ，Can I simply edit the link file， And let the cpu core to automatically download the code from external rom/ram/flash, is that possible, if we do not have the dma master design, but we still want to run code in iccm

Problems when using SweRV_fpga with V1.5 of SweRV

Hi,
I was using SweRV_fpga (https://github.com/chipsalliance/Cores-SweRV_fpga) with version 1.4 of SweRV with no problems. Everything was working fine.

When I've changed the core to SweRV 1.5, OpenOCD is failing. This is the message that I obtain when running OpenOCD:
Open On-Chip Debugger 0.10.0+dev-00530-gaf3a034b5 (2020-02-07-14:17)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1500 kHz
Info : clock speed 1500 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x00000001 (mfg: 0x000 (), part: 0x0000, ver: 0x0)
Error: Debug Module did not become active. dmcontrol=0x0
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet

Do you know which can be the reason?

Thanks,
Dani

What is the difference?

What is the difference between https://github.com/chipsalliance/Cores-SweRV and https://github.com/westerndigitalcorporation/swerv_eh1. Are they maintained by the same people?

Difference behavior for system Bus Access in dbg.sv and RISC-V External Debug Support Version 0.13.2

In section 3.12.23 of "RISC-V External Debug Support Version 0.13.2", write "sbdata0" operation will trigger the system bus write access operation. But in dbg.sv, the write or read access operation is decided by sbcs_reg[15] or sbcs_reg[20] and this seems don't match with the specification.

Unconventional mux logic

Instead of using the case statement for select encoding and having an a mux cell, may I know what is the reason for the unconventional way of doing the mux logic in this repository?

It is quite non-intuitive and does not guarantee the conditions to be mutually exclusive.

For example

//ifu_aln_ctl.sv line 565
assign f1pc_in[31:1] = ({31{fetch_to_f1}} & ifu_fetch_pc[31:1]) |
                       ({31{shift_f2_f1}} & f2pc[31:1]) |
                       ({31{~fetch_to_f1&~shift_f2_f1}} & sf1pc[31:1]);

running with stack in RAM

I have tried running on the "verilated" simulated core a simple program making a function call but hit a snag.

The program is

#include "defines.h"

#define STDOUT 0xd0580000

.section .text
.global _start
_start:
    la   sp, _sp
	
    // Clear minstret
    csrw minstret, zero
    csrw minstreth, zero

    // Set up MTVEC - not expecting to use it though 
    li x1, RV_ICCM_SADR
    csrw mtvec, x1
 
 
    // Enable Caches in MRAC
    li x1, 0x55555555
    csrw 0x7c0, x1
 
    call main
	
// Write 0xff to STDOUT for TB to termiate test.
_finish:
    li x3, STDOUT
    addi x5, x0, 0xff
    sb x5, 0(x3)
    beq x0, x0, _finish
.rept 100
    nop
.endr

	.align	1
	.globl	main
	.type	main, @function
main:
	addi	sp,sp,-256
	sw	ra,252(sp)
	sw	s0,248(sp)

.rept 7
	nop
.endr
	
	lw	ra,252(sp)
	lw	s0,248(sp)
	addi	sp,sp,256
	jr	ra
	.size	main, .-main

The link file is

OUTPUT_ARCH( "riscv" )
ENTRY(_start)

MEMORY
{
	RAM  (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 64K
}

/*----------------------------------------------------------------------*/
/* Sections                                                             */
/*----------------------------------------------------------------------*/

SECTIONS
{
  __stack_size = DEFINED(__stack_size) ? __stack_size : 4K;

  .text.init	:
  {
	*(.text.init)
	. = ALIGN(8);
  } > RAM

  .text :
  {
    *(.text.unlikely .text.unlikely.*)
    *(.text.startup .text.startup.*)
    *(.text .text.*)
    *(.gnu.linkonce.t.*)
	. = ALIGN(8);
  } > RAM

  .rodata	:
  {
    *(.rdata)
    *(.rodata .rodata.*)
    *(.gnu.linkonce.r.*)
	. = ALIGN(8);
  } > RAM

  .data	:
  {
	*(.data .data.*)
    *(.gnu.linkonce.d.*)
	. = ALIGN(8);
  } > RAM
  .sdata	:
  {
	. = ALIGN(8);
    __global_pointer$ = . + 0x800;
    *(.sdata .sdata.*)
    *(.gnu.linkonce.s.*)
    . = ALIGN(8);
    *(.srodata .srodata.*)
	. = ALIGN(8);
  } > RAM

  .sbss : {
    *(.sbss .sbss.* .gnu.linkonce.sb.*)
    *(.scommon)
	. = ALIGN(8);
  } > RAM
  .bss :
  {
	*(.bss)
	. = ALIGN(8);
  } > RAM

  _end = .;

  .stack :
  {
	_heap_end = .;
	. = . + __stack_size;
	_sp = .;
  } > RAM
}

The trace seems to imply that value 0 is read from memory and restored to ra thus the function returns not to the normal return location but to program start. A neverending loop ensues and the program is killed because the number of simulated instructions exceeds a threshold.

If rept 7 is replaced by rept 6 things run perfectly : function main is called and then the program terminates.

My interpretation is that in one case the read to ra is not actually performed from RAM but from a write buffer, while in the other case a read from RAM is performed and the simulated RAM answers 0.

I'm at a loss—how am I supposed to run programs that write to RAM?

SweRV on genesys2

I tried to run the swerv core with Configure in "SweRV_CoreMark_Benchmarking.pdf" on genesys2 fpga board, and it could successfully run the hello example through openocd;
But when I tried to run the dhrystone with "number of runs" = 1000000 through openocd, it took 334 seconds and the DMIPS was very low.

So, could somebody tell me where the question is?
The change all I made was:

1. change the constraint file
2. update the IP for genesys2 FPGA

The dryhstone code was from https://github.com/sifive/benchmark-dhrystone
I copied the makefile from hello example for dryhstone
Deleting -nostdlib and change all hello.c to dhry_1.c dhry_2.c
Thanks!

Code cleanup: fix line endings

Perforce is complaining about line endings in the 4 files below. dos2unix seems to clean them up. (Command for recursive cleanup: 'find . -type f -print0 | xargs -0 dos2unix'

• design/dmi/dmi_wrapper.v
• design/dmi/dmi_jtag_to_core_sync.v
• testbench/hex/data.hex
• testbench/hex/program.hex

Set RV_FPGA_OPTIMIZE by default?

As described in a recent paper on optimizing SweRV performance on Verilator (see under https://veripool.org/papers) there is a very large performance speedup when RV_FPGA_OPTIMIZE is set.

I would suggest setting this by default in your simulation makefiles, for all three cores.

I would also suggest it is much more likely a given user will be doing FPGA design than ASIC design, and you may want to make it always be the default for all usages and require/document -set=fpga_optimize=0 for ASIC users.

Thanks for considering.

RISCV-Compliance check - Some Fails

Hi,
I successfully run the RISC-V Compliance check (https://github.com/riscv/riscv-compliance) on the provided SweRV RTL and I was able to pass most of the tests except the following:

1. ree_rv32i.I-MISALIGN_JMP-01
2. ree_rv32i.I-MISALIGN_LDST-01
3. ree_rv32mi.breakpoint
4. ree_rv32Zifencei.I-FENCE.I-01
5. ree_rv32ui.fence_i

Unfortunately I couldn't find any information about RISC-V-Compliance check regarding SweRV.

• Regarding 1./2.
  I read that this is not needed by RISC-V spec. And also it is implementation dependent. Whenever the RTL already contains mechanism to handle misalignments, this test probably fails...
  What about SweRV implementation?

• Regarding 3
  I didn't yet analyze in detail, but I don't expect this to be really relevant

• Regarding 4./5.
  As stated in the PRM (1.1 Features):

RV32IMCZifencei_Zicsr-compliant RISC-V core with branch predictor
I would expect this test to pass...

Has anyone ever run RISC-V compliance on SweRV and can comment on the above issues?

Thanks and best regards
cr

DCCM load/store conflict situation

DCCM data outputs are forced to 0 values at he testbench.
Does this mean DCCM is not supposed to be used?

And if DCCM is in the working state, I've got a question.
Does LSU support resolving of conflicts when store and load operations are performed with the same target address? Or such situations should be resolved on the software side?

problem with the linker and undefined reference errors ?

HI !
Is there a problem with the linker when running a c code ?
My c code includes all the necessary librarys and compiles separatly without a problem but i try to run it using the core , I keep getting undefine reference error for a lot of standard c funtions example printf ? anyone else had this error ?

the riscv64-unknown-elf-ld fails during the building

DCCM max size

@aprnath ,
I see that the maximum size of DCCM is limited to 512kB. I am trying to use the SweRV for an application that needs a larger DCCM , 4 - 8 MB. How easy is it to achieve this?

Thanks!

Initialization/startup sequence and linker script for large C programs

Hello - I am trying to run simulations of some large C programs on the SweRV RTL, but figuring out the expected initialization and finish functions, linker script and any other system configuration requirements is proving to me difficult for me - exec.log shows the simulation takes an exception in the third instruction and keeps looping there. Could you please add a compilation recipe for some arbitrarily large C programs that would run on the default SweRV configuration? Thanks in advance.

the design won't synthesize in Vivado due to syntax errors

The Vivado synthetizer does not like the ' in
rden <= '0;
wren <= '0;

I don't know anything about Verilog.
The following fixes the syntax issues but I'm unsure whether this actually works :

diff --git a/design/dmi/dmi_jtag_to_core_sync.v b/design/dmi/dmi_jtag_to_core_sync.v
index aa4c19f..2d1477c 100644
--- a/design/dmi/dmi_jtag_to_core_sync.v
+++ b/design/dmi/dmi_jtag_to_core_sync.v
@@ -48,8 +48,8 @@ module dmi_jtag_to_core_sync (
 // synchronizers  
 always @ ( posedge clk or negedge rst_n) begin
     if(!rst_n) begin
-        rden <= '0;
-        wren <= '0;
+        rden <= 0;
+        wren <= 0;
     end
     else begin
         rden <= {rden[1:0], rd_en};

EH2 and EL2 are missing.

Earlier this month Western Digital announced two new cores, EH2 and EL2, in addition to the current one here, EH1: https://www.westerndigital.com/risc-v

But I don't see them in this repository, linked on that page. Where could I find these two new cores?

SWERV CPU doesn't work properly if memory interface HREADY signal is high by default

SWERV CPU doesn't work properly if memory interface HREADY signal (highlighted on the waveform) is high by default:

If HREADY is low as shown below, the CPU work fine.

Question: how to disable (bypass) data checks in cache?

I see that CPU often checks for instruction data in icache even when it's disabled by SWERV configuration (icache_enable=0). This affects overall CPU memory access performance.
Please, suggest if it's possible to bypass icache.

Add test for core & simulator benchmarking

I suggest that the SweRV repo add a "make benchmark", that runs a binary that e.g. runs CoreMark for about 30-60 seconds.

Background:

I'm using Cores-SweRV as part of the Verilator regressions, see https://github.com/verilator/verilator_ext_tests. This runs the SweRV repo's test, which is basically a hello world test. This is good to make sure that nothing simple is broken in the simulator (e.g. Verilator), or SweRV itself, and has found a few issues in both.

However, what is missing is a longer running SewRV test that can be used to benchmark the simulator, for both ensuring that the simulator does not introduce a performance bug, and as an experimental case for potential performance enhancements. I thus request a binary and "make benchmark" that would have a simulation runtime (as opposed to simulated time) in the 30-60 second range, with a tuneable number of iterations. Tuning the iterations shouldn't need to recompile the binary, as the toolchain needed to make an equivalent binary might not be easily reproducible.

What should be the longer running test? Ideally it should hit a good cross section of the CPU logic, with a somewhat realistic usage pattern (e.g. not just running reset a bunch of times). A great possibility would be the CPU is running a benchmark. If this longer running test was e.g. the core running the main loop of the coremark binary (https://github.com/eembc/coremark), this would add another benefit, namely allowing the core itself to be benchmarked as part of the same process. This would be useful for those experimenting on the core itself. This also would ensure that a reasonable amount of logic in the core is lighting up.

Thanks

access dccm through dma port

When use external dma master to read/write data from/to DCCM through dma port, it's need more cycles (up to 20 cycles if config AHB-lite bus), why need so many cycles to access? if there are some ways to speed up this operation?

thanks!

Auto increment is broken for system bus accesses of 64 bit.

Hi,

If there is an 8-byte access, the sbaddress will not auto increment. A mistake in code means that the address will be incremented by 8 if it's a 16-Byte access (illegal)

dbg.sv:272

({4{(sbcs_reg[19:17] == 3'b100)}} & 4'b1000);
should be
({4{(sbcs_reg[19:17] == 3'b011)}} & 4'b1000);

Thanks!

Issue in running the Design in vivado

Hello,

I am just trying to run swerv design on xilinx zed board using vivado and instead of running it in the debug mode using jtag and uart i want to interface this with zedboard io's.
Could you help me in this as i am unable to write firmware sequences for the swerv core in fpga or how to initialize the memory with those hardcode sequence.

Thanks

Problem with interrupts and SweRVolf

I am trying to make interrupts work in the SweRVolf SoC. The concrete objective is to make switches work by using vectorized interrupts. I am following the Swerv documentation, trying to replicate the 7 steps mentioned in section 5.5.1 with the help of the code provided in section 5.14.1. Furthermore, I have included some code of my own to integrate the support for vectorized interrupts. Nevertheless, I am having problems with the code and also I have some doubts with the guide.

1. When trying to configure interrupts, it is necessary to access the CSR address space, concretely the one shown in Table 5-13. They are located in contiguous addresses, but according to documentation, these registers are 32-bits wide. It is true that there are many reserved sections, but if I am not wrong, there exists the possibility of overlapping. I am concerned about this, because the base address loaded in MEIVT for initializing the vector table is overwritten when initializing the thresholds through MEICIDPL. Here is an example:

MEIVT 0xBC8 ==> Write on bits 10..31, 9..0 reserved
MEIPT 0xBC9 ==> Write on bits 3..0, 31..4 reserved
MEICPCT 0xBCA ==> 31..0 reserved
MEICIDPL 0xBCB ==> Write on bits 3..0, 31..4 reserved
MEICURPL 0xBCC ==> Write on bits 3..0, 31..4 reserved

Memory in little endian (initialized to all 1s)

0xBC8 | 0xBC9 | 0xBCA | 0xBCB | 0xBCC
FF FF FF FF FF

Sequence of all 0s
Write MEIVT

0xBC8 | 0xBC9 | 0xBCA | 0xBCB | 0xBCC
FF 03 00 00 FF

Write MEIPT (0x1)

0xBC8 | 0xBC9 | 0xBCA | 0xBCB | 0xBCC
FF 01 00 00 FF

Write MEICIDPL (0x2)

0xBC8 | 0xBC9 | 0xBCA | 0xBCB | 0xBCC
FF 01 00 02 FF (here overlapping is produced)

Write MEICURPL (0x3)

0xBC8 | 0xBC9 | 0xBCA | 0xBCB | 0xBCC
FF 01 00 02 03

2. The mret instruction is not working. After executing the first routine in the code (init_vector_table_rt), the pc comes back and this routine is executed again and again. When substituting mret by just ret, the code finishes, but interrupts are not working.

3. Another issue is the id of the gateway. According to the PLIC documentation, all harts in RISC-V are connected through gateways. I have supposed this id is 1, but probably this is wrong.

I attach the code as well. If you could provide some answers it would be of great help.

LedsSwitches.dis.txt
LedsSwitches.S.txt

Supporting DCCM without multi-bank Support

@aprnath ,
I am trying to use a DCCM without multiple bank access capability. The current DCCM (say DCCM_orig) interface looks like this

---

output logic dccm_wren,
output logic dccm_rden,
output logic [RV_DCCM_BITS-1:0] dccm_wr_addr, output logic [RV_DCCM_BITS-1:0] dccm_rd_addr_lo,
output logic [RV_DCCM_BITS-1:0] dccm_rd_addr_hi, output logic [RV_DCCM_FDATA_WIDTH-1:0] dccm_wr_data,
input logic [RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, input logic [RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,

---

This supports all types of unaligned access. However, I can only have a DCCM, (say DCCM_new) with memory bank structure that has the below interface.

---

output logic dccm_wren,
output logic dccm_rden,
output logic [RV_DCCM_BITS-1:0] dccm_wr_addr, output logic [RV_DCCM_BITS-1:0] dccm_rd_addr,
output logic [RV_DCCM_FDATA_WIDTH-1:0] dccm_wr_data, input logic [RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data,

---

DCCM_new originally was 64bits wide, so I can increase the width of dccm_rd_data to 64 from 32 (RV_DCCM_FDATA_WIDTH is 39 - 32 data, 7 ECC). This can support only a small subset of unaligned accesses.
Eg : A word (32- bit) access to address 0x0106 (mapped to DCCM_orig), successfully passes as the core splits this into two read accesses, one each to 0x0106 and 0x0109. that get processed simultaneously. However, a word read access to 0x0106 on DCCM_new fails.

Is it possible to configure SweRV to support DCCMs with banking structures that can support data access to only one bank at a time?

Thanks!

Questa support in Makefile for simulations

I tried running SweRV with Mentor Graphics's Questa simulator. I see testbench/flist.questa file-list, but Makefile didn't have targets for the same. I added the same and then found few minor issues in flist.questa, I have fixed and marked them with "// VW" for your kind review.

Please see if you can incorporate these changes and/o validate the same at your end.

Thanks
Srini

Makefile.txt
flist.questa.txt

D-cache to complement I-cache

To get the full performance of SweRV, I am aware that you should use the tightly coupled memories (ICCM and DCCM).
When using larger external memory, the common way is to attach them via AXI. Then you can use the I-cache for faster access to instructions. However, this option is not available for data accesses. One workaround is to use a DMA engine to transfer data into the DCCM.
A more convenient solution would be a D-cache, similar to the existing I-cache. Are there any plans to include such a feature in upcoming releases of SweRV?

Interrupt example

Hi,
I am trying to use the interrupt on the SweRV core. I am trying the following

1. Setup interrupt[1] with following features -
   standard priority order - 0x0 @ mpiccfg
   gateway configuration set to Edge-triggered, active high - 0x2 @ meigwctrl1
   set priority level for interrupt1 to 15 - 0x000F @ meipl1
   mask no interrupt - 0x0 @ meipt
   0x0 @ meicidpl
   0x0 @ meicurpl
   Enable the interrupt - 0x1 @ meie1
   machine interrupt enable - 0x800 @ mie (0x304)

2. put the system to sleep by writing 0x1 to 0x7C6(mpmc)

3. Toggle the interrupt1 bit using testbench.

I see the signal mhwakeup( in dec.tlu) get asserted, but the mhwakeup_ready does not go high since the interrupt is not enabled in the mstatus register.

What is the correct sequence of setting up interrupts and handlers? Can you please provide an example of basic interrupt handler setup and usage? The Example interrupt flows (5.14.1) seems inadequate.

Thanks,
Jagannath

Wrong assignment to enum variable from expression of different type

Hey!
Enum should be assignment only by enum type. LRM1800-2017 6.19.4: A cast shall be required for an expression that is assigned to an enum variable where the type of the expression is not equivalent to the enumeration type of the variable.
So in file design/ifu/ifu_ifc_ctl.sv need to be change two lines:
assign next_state[1] = (~state[1] & state[0] & ~reset_delayed & miss_f2 & ~goto_idle) | (state[1] & ~reset_delayed & ~mb_empty_mod & ~goto_idle);
for
assign next_state[1] = state_t'((~state[1] & state[0] & ~reset_delayed & miss_f2 & ~goto_idle) | (state[1] & ~reset_delayed & ~mb_empty_mod & ~goto_idle));

and
assign next_state[0] = (~goto_idle & leave_idle) | (state[0] & ~goto_idle) | (reset_delayed);
for
assign next_state[0] = state_t'((~goto_idle & leave_idle) | (state[0] & ~goto_idle) | (reset_delayed));
Like was done in pull request #49

flist.questa includes def.sv and hasn't moved to testbench dir

All the flist.* files except flist.questa moved from the design to testbench directory recently. However flist.questa didn't.

Also flist.questa lists the file def.sv which has been removed
design/flist.questa:$RV_ROOT/design/include/def.sv

verilator in the make file not working

Hi !
I have been trying to the make -f $RV_ROOT/tools/Makefile
and the verilator build is failing .

but when i run the verilator is installed in my ubuntu system and the commands works se proof:
mikemusasa@SE-00023761:~/Cores-SweRV$ verilator
Usage:
verilator --help
verilator --version
verilator --cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
verilator --sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
verilator --lint-only [source_files.v]...

And the error i am getting from the make file is this :

%Error: Command Failed /verilator_bin -UASSERT_ON --cc -CFLAGS '-std=c++11' snapshots/default/common_defines.vh /home/mikemusasa/Cores-SweRV/design/include/swerv_types.sv -I/home/mikemusasa/Cores-SweRV/design/include -I/home/mikemusasa/Cores-SweRV/design/lib -Isnapshots/default -Wno-UNOPTFLAT -I/home/mikemusasa/Cores-SweRV/testbench -f /home/mikemusasa/Cores-SweRV/testbench/flist /home/mikemusasa/Cores-SweRV/testbench/tb_top.sv /home/mikemusasa/Cores-SweRV/testbench/ahb_sif.sv --top-module tb_top -exe test_tb_top.cpp --autoflush
/home/mikemusasa/Cores-SweRV/tools/Makefile:85: recipe for target 'verilator-build' failed
make: *** [verilator-build] Error 127

Any help would be appriciated

Change address of programm

Hi,
i'm trying to change the location where the SwerV look for his programm to be compliant with my adress map. In your "Hello world" Example it loads his first instruction at the address 0x80000000, i try to find this value in the configs file to change it but i don't find it.
I tried to change the value of "external_prog" but i don't see any changes in the simulation, the first instruction is still loaded from the address 0x80000000.
So my question is "is it possible to change this address ? And if yes what are the changes that needs to be done in the config file ?"
Thanks in advance
MatthPouss

Issues to enable DMA for SweRV

Hi,
I am trying to enable DMA for SweRV. I did following changes in testbench/tb_top.sv

1.added following signal
logic [31:0] dma_haddr;
logic [2:0] dma_hburst;
logic [3:0] dma_hprot;
logic [2:0] dma_hsize;
logic [1:0] dma_htrans;
logic dma_hmastlock;
logic dma_hwrite;
wire dma_hresp_out;

2. port mapping
   // DMA Slave
   //---------------------------------------------------------------
   .dma_haddr ('0) replaced with ( dma_haddr ),
   .dma_hburst ('0) replaced with ( dma_hburst ),
   .dma_hmastlock ('0) replaced with ( dma_hmastlock),
   .dma_hprot ('0) replaced with ( dma_hprot ),
   .dma_hsize ('0) replaced with ( dma_hsize),
   .dma_htrans ('0) replaced with ( dma_htrans),
   .dma_hwrite ('0) replaced with ( dma_hwrite ),
   .dma_hwdata ('0) replaced with ( dma_hwdata ),

   .dma_hrdata ( dma_hrdata ),
   .dma_hresp (dma_out) replaced with ( dma_hresp_out ),
   .dma_hsel ( 1'b1 ),
   .dma_hreadyin ( dma_hready_out ),
   .dma_hreadyout ( dma_hready_out ),

3. added instance
   ahb_sif o_ahb_dma (

.HWDATA(dma_hwdata),
.HCLK(core_clk),
.HSEL(1'b1),
.HPROT(dma_hprot),
.HWRITE(dma_hwrite),
.HTRANS(dma_htrans),
.HSIZE(dma_hsize),
.HREADY(dma_hready),
.HRESETn(reset_l),
.HADDR(dma_haddr),
.HBURST(dma_hburst),

.HREADYOUT(dma_hready),
.HRESP(dma_hresp),
.HRDATA(dma_hrdata)

);

I have DMA controller (master) to drive read or write requests into ICCM/DCCM

after all , ran verilator and got hello world but DMA is not enable as ICCM and DCCM donot getting any data.

Here is GTKwave for reference

Please help me, to enable DMA for SweRV

Thanks & Regards
Rajoo

ifu interface access illegal address

Ifu interface will access illegal address while cpu is running，But does not affect the function.
For example，the 0x0-0x30 is illegal address

after analysis，we found that the BP predicted an incorrect address. Can I solve this problem by set the register?

Performance of SWERV EH1

https://content.riscv.org/wp-content/uploads/2019/04/RISC-V_SweRV_Roadshow-.pdf
Page 11, it is said using optimized strcpy function we could get 2.9 DMIPS/MHz.
Where can I find the optimized strcpy function? Is it open-source ?

SweRV VLNV

As part of packaging the SweRV EH1 core, I'm trying to figure out what would be the correct VLNV identifier. For those unaware of VLNV, it's an classification system for IP cores, stemming from the IP-XACT standard and stands for Vendor Library Name Version.

Vendor would be chipsalliance.org and version would be 1.1 in this case, but I'm not sure about the library and name parts. My two proposals are

library = cores
name = SweRV_EH1

or

library = SweRV
name = EH1

The first one is based on that it belongs to the chipsalliance Cores library. The second one is because I have seen SweRV itself being referred to as a library of processors.

Anyway, both are fine with me, but I would like some input from the designers and those with a roadmap

DCCM coherncy issue

Unfortunately I can't reopen issue #36, so I've created this one as to continue the thread.

external interrupt handler return problem

When writing External interrupt handler in assembly language, I follow advice from the datasheet:

However the CPU does not return on MRET isntruction to the main code. It continues execution of the instructions below MRET. One workaround is to place about 20 NOP instructions before MRET. In that case the CPU executes MRET as expected - it jumps to the address stored in MEPC.

Please, advice whether I miss something.

All pdf file in the doc folder can not be shown and downloaded。The error message is "Sorry, this file is invalid so it cannot be displayed."

Add GitHub repository topics

Hello SweRV community! 👋

It would be great to add some relevant GitHub topics to this repository. It may bring more people and help with promoting this core as well as related open-source stuff. What do you think? 🤔

About OpenOCD extensions

Hi, all,

It seems standard OpenOCD can not access ICCM/DCCM, how to enable it?

There some information mentioned here, Anyone has the detail information?

Thanks.

SweRV_CoreMark_Benchmarking.pdf Page 7:
"
We added abstract commands (based on RISC-V Debug
specification 0.13) to access the ICCM and DCCM
(leverage and extend CREX OpenOCD work)
"

$readmem file address beyond bounds of array

Hi,

I try to simule a small file.c that it uses standard libraries (stdio).
For example to use printf from stdio:

#include <stdio.h>
#include "defines.h"
#define ITERATIONS 1
extern int STACK;
int main();


int mult() {
        int a=1000,b=3;
        return a*b;
}

/*********************MAIN************************/

int  main() {
        int result;
        result = mult();
        printf("printf" );
	
return 0;

}

I needed to change the linker script like this :

_OUTPUT_ARCH( "riscv" )
ENTRY(_start)

SECTIONS
{
 _start = .;
    . = 0;
  .text   : { *(.text*) }
 _end = .;
  .data  :  ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
}
```_

and now I have a problem I think with verilator when I try t0 simule : 
`VerilatorTB: Start of sim`
`%Error: program.hex:4097: $readmem file address beyond bounds of array`

I would like to know how configure more memory to execute my test? 

Thanks,

cebaut :)

freeRTOS on SweRB

All,
Because the current test bench is too simple for me to learn the sweRV, thus I use FreeRTOS as the target to learn how to control this great design. With small modification of original test bench, the simple demo from FreeRTOS can be tested using RTL simulation.
It's a good start for me and hope it can also help others to get more familiar with sweRV.

github path:
https://github.com/ycyang0508/FreeRTOS_on_SweRV
Ya-Chau

Apostrophe incorrectly introduced into the licence header ifu_ic_mem.sv

// Copyright 2019 Western Digital Corporation or it's affiliates.
This line appears in license header of ifu_ic_mem.sv
The apostrophe has been introduced since the previous version I have.
There should not be an apostrophe here.

Testbench does not verilate

The Verilator external test suite is breaking on the SweRV test, and this time I don't believe it is a Verilator regression:
https://travis-ci.com/verilator/verilator_ext_tests/jobs/228899219

It appears that commit 0dacc978 moved finished outside of a macro block that was probably there to get around this issue in the first place. Now Verilator complains that it is defined twice.

question regarding how to run own C code on the core

Hi,
I have managed to perform all of the steps of the read me document and test the hello World.
I was wondering on what is the correct way to run my own written c program on the SweRV core ?

i wrote a simple c code called testar that is suppose to print out a simple text " the test worked " .
I put my C code in testbench/ asm .
I tried the command make -f $RV_ROOT/tools/Makefile program.hex TEST=testar

is this the right way to go abou it , even for big C codes ?

SweRV build breaks on latest Verilator

Just a heads-up. I'm working on head-to-head Verilator CI with external projects and found that the latest Verilator tosses some width warnings on the SweRV build:
https://www.veripool.org/issues/1483-Verilator-Make-verilator_ext_tests-head-to-head

I'm sure this isn't urgent, so I can touch things up but I won't be able to get to it for a week or so. I thought I'd post here in case someone cares before then.

Code cleanup: replace spurious tabs with spaces

Lots of files use both tabs and spaces to indent. If you don't have the same tab setting as the last engineer who touched the code then the indenting breaks. Can we replace the tabs with spaces?

It looks like 4 spaces is what is used for the file's I've looked at.

Here's an example code segment taken at random:

Improve reference to espresso on front page?

I assume you mean espresso the heuristic logic minimization tool, but it could be made clearer; is there a certain version required? Where do we get it?

A good number (...most?) people won't hear "espresso" and immediately think "Oh yeah, logic minimization!" :)

Software breakpoints with OpenOCD + GDB

When connecting OpenOCD I get the following warning:

Info : datacount=2 progbufsize=0
Warn : We won't be able to execute fence instructions on this target. Memory may not always appear consistent. (progbufsize=0, impebreak=0)

With icache enabled is there any way of reliably setting a SW breakpoint? Build options via swerv.config? I imagine this would require a fence instruction to be issued to flush cache but there's no program buffer to do so...

The custom CSR (0x7C4) seems that it would work via 'expose_csr' on OCD but initial results show inconsistent behavior

RV core With AHB bus will cause bug when send read operation

In the latest test, RV core in my soc envirent will cause NMI err.

The detail is because the RV core send a 64bit width read transation of AHB bus, while I only wirte an "unsigned int read regitster" code in my c file.
And ,the register I want read is right the last register of one module, so this 64 bit read cause slverr back, and then the RV core get into MNI interrupt.