Comments (1)
With the current architecture, we need atleast 2 banks to support unaligned read accesses. There is no way to support unaligned access, as designed, with single bank DCCM.
from cores-veer-eh1.
Related Issues (20)
- fpga_optimize cannot be set to 0 in swerv_config HOT 1
- openocd timeout occurs when trying to load elf file using command 'load_image'. HOT 7
- Try running multi thread program on swerv EH1 core HOT 2
- CoreMark test score HOT 2
- Unable to replicate performance improvement achieved by using different target values HOT 1
- Usage scenarios of different DFFs
- GHR refresh HOT 1
- Fusesoc's sim target is deprecated HOT 10
- Question about pipeline FF enable signals
- facing issues when C code size goes beyond 8KB HOT 1
- Coremark for new extension
- Repo renaming HOT 2
- Blocking Loads/DMA disable
- OpenOCD download to ICCM/DCCM failed. HOT 1
- The new feature of verilator stops building procession HOT 2
- Formal Verification of SweRV EH1 using riscv-formal
- GCC version in Makefile HOT 4
- $readmem file address beyond bounds of array HOT 8
- Timing violations with Vivado HOT 4
- slip in dec_decode_ctrl
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