fasm2bels is a tool designed to take a FASM file into Vivado.
It does this by generating a file describing the BEL connections (techmapped Verilog) and TCL commands for Vivado which lock the BEL placements.
This makes it possible to perform simulation and analysis of a FASM file inside Vivado.
In the absence of bugs, it is expected that after consuming the BEL connections and TCL constraints Vivado will produce a bitstream identical to the bitstream the FASM file would generate.
After cloning this repo, run the following commands:
make env- this should work with many versions of python3 and above.make build
There are a set of tests to prevent regression and verify that all the functionalities of fasm2bels correctly work.
Before running the test, export the following environmental variables to have a properly working interchange files generation step:
export CAPNP_PATH=$(pwd)/third_party/capnproto-java/compiler/src/main/schema/
export INTERCHANGE_SCHEMA_PATH=$(pwd)/third_party/fpga-interchange-schema/interchange
Once the environment is ready, run the python tests:
make test-py- It takes a few minutes to run all the tests (22).
An OK should appear at the bottom of the terminal run if successful.
python3 -mfasm2bels <options> <verilog> <tcl>
Required arguments are:
--connection_database- Path to connection database for part--db_root- Path to prjxray database for part--part- FPGA part--fasm_file- Path to FASM file to process- verilog - Path to verilog file to write
- tcl - Path to TCL file to write
The first time you run it you will not have a connection database for the part. Provide a name for this parameter such as ./basys3.db and the program will generate the database the first time you run. On subsequent runs you can then specify that filename and avoid re-building the database each time.
Here is an example run of the process:
python3 -mfasm2bels --connection_database mydb \
--db_root ~/prjxray/database/artix7 \
--part xc7a35tcpg236-1 \
--fasm_file file_name.fasm \
file_name.v file_name.tcl
Once the verilog and TCL is generated, it should be importable to Vivado with a script roughly like:
create_project -force -part {part} design design
read_verilog {bit_v}
synth_design -top {top}
source {bit_tcl}
set_property IS_ENABLED 0 [get_drc_checks {{LUTLP-1}}]
place_design
route_design
Timing constraints should be provided as needed, along with other property modifications as needed for the design. These properties are not embedded in the bitstream, so must be supplied external.
Examples:
set_property CFGBVS VCCO [current_design]set_property CONFIG_VOLTAGE 3.3 [current_design]
- SLICEL (all)
- SLICEM (all)
- RAMB18/RAMB36 (BRAM only, no FIFO support)
- IOB (limited IOSTANDARDs)
- IOI
- IDELAY
- IDDR/ISERDES
- ODDR/OSERDES
- CLK_HROW_*
- CLK_BUFG_*
- PLLs
- PSS
- MMCMs
- BUFR/BUFMR and other clock buffers
- DSP
![dependabot-preview[bot] avatar](https://avatars.githubusercontent.com/in/2141?v=4 "dependabot-preview[bot]")
React
Typescript
Django
Laravel
Facebook
Microsoft
Google
Alibaba
D3
Tencent