clesav/yasimavr

Yet another simulator for Microchip AVR microcontrollers, inspired from simavr

yasimavr

Yet another simulator for Microchip AVR microcontrollers, inspired from simavr

_yasimavr is a simulator for AVR 8-bits microcontrollers. It is mainly aimed at the Mega0 and Mega1 series (ATmega80x-160x-320x-480x and others) with a possibility to work with the "classic" series. (ATMega48/88/168/328 and others)

It is composed of 2 layers:

• a C++ layer for the core API and the various peripheral simulation models
• a Python layer to handle the configuration, utilities, data recording, and external components

Installation

Prerequisites:

• Python (version >=3.7) and PIP
• For Ubuntu, libelf is required: sudo apt-get install libelf-dev

Install:

• execute: pip install yasimavr

The python bindings for the C++ librairies are built with the SIP tool from RiverbankComputing (https://www.riverbankcomputing.com)

Thanks

Quite a few ideas in this software - and even big chunks of code - originate from simavr. (https://github.com/buserror/simavr) Big thanks to the simavr authors for this great tool !

Supported IOs

• GPIO
• SPI
• TWI
• USART

Supported Cores

The package includes a predefined set of MCU models:

• ATMegaxx8 series (ATMega48/88/168/328)
• ATMega 0-series (ATMega808/809/1608/1609/3208/3209/4808/4809)

Other device models can be easily simulated by creating a YAML config file. A template is provided, and the example _atgiga4809 shows how to load and use a customised device configuration. New simulation models for peripherals can be created in Python or C++ using the provided API.

Features

• Real-time/Fast mode : yasimavr can try to sync the simulated time with system time or run as fast as possible
• AVR-GDB integration : yasimavr can acts as a GDB backend stub, with support for breakpoints and watchpoints
• VCD export : yasimavr can export traces of pin states, GPIO ports, interrupt vectors, memory locations or generic signals in Value Change Dump (VCD) files
• MCU dump : at any point of the simulation, yasimavr can create a snapshot of the state of the MCU model, including all registers and memories and save it in a text file.
• "Zombie" mode : yasimavr can directly interact with simulated peripherals by acting as the CPU. This is useful to verify customised peripheral models or a test script.
• Probing : yasimavr can read/write CPU registers or memories on-the-fly. This is useful to force the firmware into certain branches for example, improving test coverage.

How to use

_yasimavr can be used as a Python package to run a prepared simulation script. (See the examples for how it looks like)

It also supports direct command line use:

• python -m yasimavr [options] [firmware]

For the list of command line options, execute python -m yasimavr -h

Some simple script examples are available here: https://github.com/clesav/yasimavr/tree/main/examples

Documentation

The documentation is still a work in progress but will be progressively completed. The online version, including an API reference, can be read on the Read the Docs:

• [Development documentation] http://yasimavr.readthedocs.io/en/latest/
• [Stable documentation] http://yasimavr.readthedocs.io/en/stable/

yasimavr's Issues

core API changes part 2

Simulation run script

Creation of a script to run simulation with a "simavr-like" command line

Class renaming and namespacing

Getting rid of the AVR_* prefix and instead using an optional namespace (by #define macro)
For bindings, no change, the generated python modules already act as namespaces.
Also some improved consistency of class naming.

Addition of analog features

Analog features to add:

• Addition of Analog Comparator peripheral.
• Possibility to have several ADC/AC peripherals.
• Redesign of VREF required to have several references for the peripherals
• Adding some of the unsupported features in M0 ADC: freerun and ASDV.

core API changes

Clean up of the core API overdue:

• simplification of CycleManager
• addition of regbit_compound_t (to represent a single field split across several registers)
• improvement of register reading/writing for speedup
• simplification of interrupt handling
• various argument const & reference missing

Changes to signal API

The current signal API needs rework :

• copy/move semantics to ensure links between signal and hooks remain consistents
• The data() function is not developed (and currently unused). Split between two signal classes: a base stateless AVR_Signal and a AVR_DataSignal that stores the data travelling in signal notifications. That will be usefull for analog features and async triggers modelling.
• invert data and index arguments in raise() : 'data' is much more useful and 'index' is meant to be optional anyway.

ctor/dtor consolidation

Consolidation of constructor & destructors
dealing with move semantics

Addition of simulation model dump

Adding a facility for dumping data on the device model: all registers, memory content, pin state, and more...

M0 architecture renaming

Renaming of M0-specific elements to XT for consistency with new attiny 0/1/2 series

New device library

Reimplementation of device library structure

Custom config loading

Improvement of the device library modularity and ability to load from an arbitrary config file outside of the library.

AVR_ArchAVR_DeviceConfig not constructible in Python

Exception raised when loading a ATmeg328 model due to AVR_ArchAVR_DeviceConfig not constructible

Classic timer model compare outputs not working

TCB model not counting