clesav/yasimavr

Yet another simulator for Microchip AVR microcontrollers, inspired from simavr

yasimavr's Issues

New device library

Reimplementation of device library structure

M0 architecture renaming

Renaming of M0-specific elements to XT for consistency with new attiny 0/1/2 series

core API changes part 2

Custom config loading

Improvement of the device library modularity and ability to load from an arbitrary config file outside of the library.

Classic timer model compare outputs not working

Class renaming and namespacing

Getting rid of the AVR_* prefix and instead using an optional namespace (by #define macro)
For bindings, no change, the generated python modules already act as namespaces.
Also some improved consistency of class naming.

Changes to signal API

The current signal API needs rework :

• copy/move semantics to ensure links between signal and hooks remain consistents
• The data() function is not developed (and currently unused). Split between two signal classes: a base stateless AVR_Signal and a AVR_DataSignal that stores the data travelling in signal notifications. That will be usefull for analog features and async triggers modelling.
• invert data and index arguments in raise() : 'data' is much more useful and 'index' is meant to be optional anyway.

Addition of analog features

Analog features to add:

• Addition of Analog Comparator peripheral.
• Possibility to have several ADC/AC peripherals.
• Redesign of VREF required to have several references for the peripherals
• Adding some of the unsupported features in M0 ADC: freerun and ASDV.

ctor/dtor consolidation

Consolidation of constructor & destructors
dealing with move semantics

TCB model not counting

Addition of simulation model dump

Adding a facility for dumping data on the device model: all registers, memory content, pin state, and more...

AVR_ArchAVR_DeviceConfig not constructible in Python

Exception raised when loading a ATmeg328 model due to AVR_ArchAVR_DeviceConfig not constructible

Simulation run script

Creation of a script to run simulation with a "simavr-like" command line

core API changes

Clean up of the core API overdue:

• simplification of CycleManager
• addition of regbit_compound_t (to represent a single field split across several registers)
• improvement of register reading/writing for speedup
• simplification of interrupt handling
• various argument const & reference missing