cp024s/100-days-of-rtl

probable journey of RTL coding ft. Chandra Prakash

Chandra Prakash's GitHub profile

He is an Engineer, a lifelong learner, a passionate RTL design enthusiast, an embedded IoT project developer, and a contributor. His area of interest lies in Computer architecture and VLSI design & Verification. Currently, he is a final-year student at PSG Institute of Technology and Applied Research, Coimbatore. Currently, he is also a trainee at Maven Silicon, Bengaluru. He is also searching for RTL design, SoC design, Verification Engineer roles

A passionate RTL Deisgn Engineer, Who is an Enigma wrapped by a mystery inside a Paradox

---

🤵🏻‍♂️ About Me

🔭 I'm currently working on RTL Deign (verilog, System Verilog, UVM)

👬 I'm looking to collaborate with people with same ideas of myself, developing projects on Verilog and VHDL

🌱 Im currently Gaining knowledge on Advanced digital design, Static timing analysis, Verilog HDL, FPGA architecture, CMOS fundamentals, Perl scripting, RISC V processor, ASIC verification methods, System verilog, Verification planning, Assertion based verification, Universal verification method and DFT.

💭 Ask/Talk to me about #RTLdesign #digitaldesign #socdesign #verification

✉️ How to reach me [email protected]

⚡Fun Fact: The name "Verilog" is a portmanteau of the words "verification" and "logic". This is because Verilog is a hardware description language (HDL) that is used to describe digital systems at the register transfer level (RTL). RTL is the level of abstraction where data is transferred between registers, and Verilog is used to describe the logic that controls this data transfer! 🧮💻👩‍💼

Tools and Skills

HDLs : Verilog, VHDL
HVL : System Verilog
Languages : C language, Python, Perl
Tools : Xilinx Vivado, Mentor Graphics ModelSim, Siemens QuestaSim, Intel Quartus
Placement & Routing : Cadence Virtuoso
Verification : UVM, SystemVerilog Assertions, Formal Verification
Protocols : I2C, UART, RS232, SPI, AXI, APB, AMBA, DDR, PCIe

📥 Recent Repo

100 Days of RTL

• Designing: Creating diverse digital hardware modules, ranging from simple components to more complex systems.
  
• Coding: Implementing RTL designs using languages like Verilog and VHDL, refining my coding skills along the way.
  
• Simulating: Verifying and testing the designs using simulation tools to ensure their correctness and functionality.
  
• Documenting: Sharing insights, challenges, and lessons learned daily, fostering a supportive learning community.
  (currently working)

Perl - A Zero to master

• Master Perl in 50 Days: A Structured Learning Program 🚀
• Ready to become a Perl expert? This 50-day program is your path to mastering Perl programming, from the basics to advanced topics. Whether you're a newbie or experienced developer, follow our daily plan, complete exercises, and work on real projects to build your Perl skills. Join us on this coding journey!
  #perl #programming #learnperl

📊 Stats:

---

Thank you for visiting my GitHub profile. Together, let's push the boundaries of digital design and create innovative solutions that shape the future of technology.