csail-csg/pyverilator

Python wrapper for verilator model

pyverilator's Issues

PyVerilator 0.7.0 (expected initializer before ‘VL_MT_UNSAFE’) inside Docker

I am trying to use PyVerilator 0.7.0 inside a Docker container and I am getting the following error:

error: expected initializer before ‘VL_MT_UNSAFE’
 void vl_finish (const char* filename, int linenum, const char* hier) VL_MT_UNSAFE {
                                  ``                                    ^
cc1plus: warning: unrecognized command line option ‘-Wno-parentheses-equality’

However, I tried switching into version 0.1.0 and the error is not there and my flow is working fine. Let me know if you need anything else to help you track the issue.

Internal signals don't work after Verilator update

pyverilator finds internal signals by parsing VL_SIG* lines in an .h file generated by verilator. The most recent version of verilator looks like it doesn't use the VL_SIG* macros anymore. Instead it, for an 8-bit signal, it produces a line like the one below:

CData/*7:0*/ parent_module__DOT__in_reg;

pyverilator should also look for this format as well.

test_pyverilator_finish_2_same_files fails

The test test_pyverilator_finish_2_same_files (https://github.com/csail-csg/pyverilator/blob/master/pyverilator/tests/test_pyverilator.py#L633-L692)
fails because sim_1 and sim_2 both load the same shared object and the verilator gotFinish uses a global variable to track if the simulator has finished. Once one finishes, both sims see gotFinish to be true.

There are three possible solutions:

1. Produce uniquely named so files for each sim
2. Make copies of so files whenever they are opened.
3. Use dlmopen to open a copy of the shared object (see the dlmopen branch https://github.com/csail-csg/pyverilator/tree/dlmopen)

I got the dlmopen solution working, but its messy, and I don't know if it will work on other machines. I'll think about this problem more before making any changes.

‘flushCall’ is not a member of ‘Verilated’

I am trying to use pyverilog with the register files generated with peakRDL-verilog (https://github.com/hughjackson/PeakRDL-verilog) and I am getting the following error.

g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -fPIC -shared --std=c++11 -DVL_USER_FINISH -std=gnu++14 -Os -c -o pyverilator_wrapper.o ../obj_dir/pyverilator_wrapper.cpp
../obj_dir/pyverilator_wrapper.cpp: In function ‘void vl_finish(const char*, int, const char*)’:
../obj_dir/pyverilator_wrapper.cpp:56:24: error: ‘flushCall’ is not a member of ‘Verilated’
56 | Verilated::flushCall();
| ^~~~~~~~~
make: *** [Vbasic_rf.mk:60: pyverilator_wrapper.o] Errore 1

Add ability to build multiple verilog files and set top module

Currently it doesnt seem like PyVerilator supports providing explicit lists of Verilog files to pass down to Verilator, or setting the top module explicitly. Verilator will only find the files automatically if they are of the same name as the modules being searched for, which is not always the case. Is there any plan to support these features in PyVerilator?

I've attached an example Verilog codebase generated by Xilinx Vivado HLS 2019.2 where some utility modules are placed in regslice_core.v. The correct way to verilate this project is:

/usr/bin/verilator_bin -Wno-fatal -Mdir . --CFLAGS '-fPIC --std=c++11' --trace --trace-depth 2 --cc Thresholding_Batch_0_Thresholding_Batch_0.v regslice_core.v --top-module Thresholding_Batch_0_Thresholding_Batch_0 --exe pyverilator_wrapper.cpp

However, building from PyVerilator fails:

[example.zip](https://github.com/csail-csg/pyverilator/files/4598719/example.zip)
In [2]: pyverilator.PyVerilator.build('Thresholding_Batch_0_Thresholding_Batch_0.v')                                                                  
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86: Cannot find file containing module: regslice_both
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86: This may be because there's no search path specified with -I<dir>.
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86: Looked in:
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       regslice_both
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       regslice_both.v
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       regslice_both.sv
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       /tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd/regslice_both
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       /tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd/regslice_both.v
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:86:       /tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd/regslice_both.sv
%Error: Thresholding_Batch_0_Thresholding_Batch_0.v:100: Cannot find file containing module: regslice_both
%Warning-WIDTH: Thresholding_Batch_0_Thresholding_Batch_0.v:171: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.
%Error: Exiting due to 10 error(s)
%Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal -Mdir /tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd --CFLAGS '-fPIC --std=c++11' --trace --trace-depth 2 --cc Thresholding_Batch_0_Thresholding_Batch_0.v --exe /tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd/pyverilator_wrapper.cpp
---------------------------------------------------------------------------
FileNotFoundError                         Traceback (most recent call last)
<ipython-input-2-30fd53adebef> in <module>
----> 1 pyverilator.PyVerilator.build('Thresholding_Batch_0_Thresholding_Batch_0.v')

/workspace/pyverilator/pyverilator/pyverilator.py in build(cls, top_verilog_file, verilog_path, build_dir, json_data, gen_only, trace_depth)
    455                 return None
    456 
--> 457         with open(verilator_h_file) as f:
    458             for line in f:
    459                 result = search_for_signal_decl('IN', line)

FileNotFoundError: [Errno 2] No such file or directory: '/tmp/Thresholding_Batch_0_Thresholding_Batch_0-jfo1mavd/VThresholding_Batch_0_Thresholding_Batch_0.h'

No tags for more recent versions

I noticed that you don't have pypi releases or github tags any versions beyond 0.1.0, but when I install the latest from the master branch from github with pip, I get that the installed version is 0.7.0... Do you plan on doing another release (as either a tag or on pypi) with newer versions of the code.

I ask because, this project is a dependency of my project (https://github.com/Xilinx/logicnets), but it also depends on more recent features than what is available in pypi. It would be nice to be able to specify that dependency in terms of a version number, but I cannot do that right now.

Do you plan on making more releases for this project?

Why does PyVerilator explicitly check for .v extension on files

Why does PyVerilator explicitly check for the .v extension on files?
Is there a good reason for this?

here is the line:
https://github.com/csail-csg/pyverilator/blob/master/pyverilator/pyverilator.py#L409

what if you call your source files .sv for system verilog ? or .txt?
It shouldn't matter right?

Crash on start_vcd_trace

On both linux and mac (python 3.7 and 3.8) all examples seg fault. This happens upon calling start_vcd_trace. I was able to trace down the crash to where the init callbacks in top->trace(tfp,99) is called in the C code. The crash happens in Top::traceInit: the userthis pointer seems to be corrupt! Unfortunately I was not able to get any further with pinpointing the cause.

Verilator version: master
PyVerilator: master

Verilator now has built in support for Python

You guys may wanna check this out:
https://github.com/patstew/verilator/tree/python/examples/make_python
Verilator now has built in support for Python. I think its gonna get merged into master in the next release.

Catch-all exception handlers break Ctrl+C

This block:

                try:
                    # try to call collection_set()
                    obj.collection_set(value)
                except:
                    raise TypeError("Item '%s' can not be set" % name)

and this one:

            try:
                obj.collection_set(value)
            except:
                raise TypeError("Item '%s' can not be set" % name)

cause issues with keyboard interrupts:

Traceback (most recent call last):
  File "/build/pyverilator/pyverilator/pyverilator.py", line 187, in __setattr__
    obj.collection_set(value)
  File "/build/pyverilator/pyverilator/pyverilator.py", line 326, in collection_set
    self.write(value)
  File "/build/pyverilator/pyverilator/pyverilator.py", line 323, in write
    self.write_function_and_args[0](*self.write_function_and_args[1:], value)
  File "/build/pyverilator/pyverilator/pyverilator.py", line 652, in _write_32
    self._post_write_hook(port_name, value)
  File "/build/pyverilator/pyverilator/pyverilator.py", line 670, in _post_write_hook
    self.eval()
  File "/build/pyverilator/pyverilator/pyverilator.py", line 707, in eval
    fn.argtypes = [ctypes.c_void_p]
KeyboardInterrupt

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "_objects/rv32.v/rvcore.pyverilator.py", line 125, in <module>
    main()
  File "_objects/rv32.v/rvcore.pyverilator.py", line 122, in main
    sim.run(args.ncycles)
  File "_objects/rv32.v/rvcore.pyverilator.py", line 88, in run
    self.tick()
  File "_objects/rv32.v/rvcore.pyverilator.py", line 49, in tick
    self.sim.io.CLK = 1
  File "/build/pyverilator/pyverilator/pyverilator.py", line 189, in __setattr__
    raise TypeError("Item '%s' can not be set" % name)
TypeError: Item 'CLK' can not be set

Could these except: be change to catch a specific error, instead of any exception? Maybe the Signal class should have a generic collection_get that throws an error that Input would override

pyverilator does not work with latest verilator

I have a program (from https://github.com/namin/bluespec-sandbox) that works with verilator 4.200 but not verilator 4.218.

The error is

clang++  -I.  -MMD -I/usr/local/Cellar/verilator/4.218/share/verilator/include -I/usr/local/Cellar/verilator/4.218/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fbracket-depth=4096 -fcf-protection=none -Qunused-arguments -Wno-bool-operation -Wno-tautological-bitwise-compare -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -fPIC -shared --std=c++11 -DVL_USER_FINISH  -std=gnu++14 -Os -c -o pyverilator_wrapper.o ../obj_dir/pyverilator_wrapper.cpp
../obj_dir/pyverilator_wrapper.cpp:113:14: error: expected ';' after top level declarator
uint32_t get_&RDY_put(Vmachine01* top){return top->&RDY_put;}
             ^
             ;
1 error generated.
make: *** [pyverilator_wrapper.o] Error 1
Traceback (most recent call last):
  File "/Users/namin/code/blu/bluespec-sandbox/testbench.py", line 3, in <module>
    sim = PyVerilator.build('machine01.v')
  File "/Users/namin/opt/anaconda3/lib/python3.9/site-packages/pyverilator/pyverilator.py", line 493, in build
    call_process(make_args, quiet=quiet)
  File "/Users/namin/opt/anaconda3/lib/python3.9/site-packages/pyverilator/pyverilator.py", line 345, in call_process
    subprocess.check_call(args)
  File "/Users/namin/opt/anaconda3/lib/python3.9/subprocess.py", line 373, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['make', '-C', 'obj_dir', '-f', 'Vmachine01.mk', 'LDFLAGS=-fPIC -shared']' returned non-zero exit status 2.

Let me know if I can provide more information.

Thanks!