deepware-ai,Deepware,github

accdnn

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

acceltran

[TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers

activecore

Hardware generation library based on "MLIP cores" (microarchitectural programmable templates)

aladdin

A pre-RTL, power-performance model for fixed-function accelerators

annette

ANNETTE - Accurate Neural Network Execution Time Estimation

Antares: an automatic engine for multi-platform kernel generation and optimization. Supporting CPU, CUDA, ROCm, DirectX12, GraphCore, SYCL for CPU/GPU, OpenCL for AMD/NVIDIA, Android CPU/GPU backends.

approximate-spmv-topk

Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

autosa

AutoSA: Polyhedral-Based Systolic Array Compiler

awesome-edge-machine-learning

A curated list of awesome edge machine learning resources, including research papers, inference engines, challenges, books, meetups and others.

awesome-embeded-ai

收集关于嵌入式领域的机器学习算法实现的进展、相关论文和文章、开发库等，帮助初学者快速了解、学习和入门嵌入式领域的机器学习。CC-BY-NC-SA 4.0。

awesome-model-quantization

A list of papers, docs, codes about model quantization. This repo is aimed to provide the info for model quantization research, we are continuously improving the project. Welcome to PR the works (papers, repositories) that are missed by the repo.

awesome-pruning

A curated list of neural network pruning resources.

awesome-real-time-ai

This is a list of awesome edgeAI inference related papers.

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

barvinn

BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/

bismo

BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing

blockminifloatmac

Block minifloat MAC unit for single block GEMM

bnna

bnn accelerator

bragghls

PyTorch model to RTL flow for low latency inference

brevitas

Brevitas: quantization-aware training in PyTorch

bsg_manycore

Tile based architecture designed for computing efficiency, scalability and generality

cfu-playground

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM).

charm

CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture (Full Paper accepted to FPGA2023!)

chip-knn

[FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs

chip-multi-processor-system-based-on-cardinal-bidirectional-ring-network-on-chip

EE577b-Course-Project

cmix-nn

CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices

cnn-fpga

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

configurable-systolic-systemverilog

Systolic Implementation

convolution_network_on_fpga

CNN acceleration on virtex-7 FPGA with verilog HDL

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