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pe_coprocessor

pipecnn

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

pulp-nn

q-mann

Quantized Memory-Augmented Neural Networks (AAAI-18)

quantlab

quantlib

rbe

Reconfigurable Binary Engine

seasynth

A synthesize-able CNN accelerator based on systolic arrays 🌊

simpletpu

A FPGA Based CNN accelerator, following Google's TPU V1.

sodla

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

sodla-docs

Documentation for soDLA project.

somnia

Learn NVDLA by SOMNIA

sonn

A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.

spinalhdl_cnn_accelerator

CNN accelerator implemented with Spinal HDL

sycl

Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

sycl-building-blocks

systemc-compiler

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

systolic-array

A DSL for Systolic Arrays

tengine

Tengine is a lite, high performance, modular inference engine for embedded device

tf2

An Open Source Deep Learning Inference Engine Based on FPGA

tim-vx

Verisilicon Tensor Interface Module for OpenVX

training-mixed-precision-quantized-networks

This repository containts the pytorch scripts to train mixed-precision networks for microcontroller deployment, based on the memory contraints of the target device.

transpyle

HPC-oriented transpiler for C, C++, Cython, Fortran, OpenCL and Python.

usystolic-sim

A systolic array simulator for multi-cycle MACs and varying-byte words

vitis-ai

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

vitis-tutorials

vitis_accel_examples

Vitis_Accel_Examples

vitis_notebooks

vmware-verilog-jit-compiler-cascade

A Just-In-Time Compiler for Verilog from VMware Research

xnnpack

High-efficiency floating-point neural network inference operators for mobile, server, and Web