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how_to_optimize_in_gpu

This is a series of GPU optimization topics. Here we will introduce how to optimize the program on the GPU in detail. I will introduce several basic kernel optimizations, including: elementwise, reduce, sgemv, sgemm, etc. The performance of these kernels is basically at or near the theoretical limit.

intel-edge-ai-for-iot-developers-nanodegree-program

Leverage the Intel® Distribution of OpenVINO™ Toolkit to fast-track development of high-performance computer vision and deep learning inference applications, and run pre-trained deep learning models for computer vision on-premise. You will identify key hardware specifications of various hardware types (CPU, VPU, FPGA, and Integrated GPU), and utilize the Intel® DevCloud for the Edge to test model performance on the various hardware types. Finally, you will use software tools to optimize deep learning models to improve performance of Edge AI systems. - Source

intel-ia-neon

iob-versat

Coarse Grained Reconfigurable Array

learning-nvdla-notes

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

lenet5_hls

FPGA Accelerator for CNN using Vivado HLS

libposit

A library for working with the posit number type.

lina

A high-level performance analysis tool for FPGA-based accelerators

magicube

Magicube is a high-performance library for quantized sparse matrix operations (SpMM and SDDMM) of deep learning on Tensor Cores.

mann-fpga

Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA (DATE-19)

marlann

Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks

mensa.wip

Micro tensor accelerator

mgrn

Memory-Gated Recurrent Networks (AAAI 2021)

mixed_signal_mmwave_edge_accelerator

mkl-dnn

mlflow

Open source platform for the machine learning lifecycle

mmm_sa_2by2_posit_4_0

This repository contains a Matrix-Matrix-Multiply unit performed by a 2x2 systolic array and posit<4,0> numbers

mvu

Neural Network accelerator powered by MVUs and RISC-V.

n2s3_examples

Examples of projects using the n2s3 neuromorphic accelerator

nacu

This is a repository for the "NACU: A Non-Linear Arithmetic Unit for Neural Networks"

ne16

Neural Engine, 16 input channels

nemo

NEural Minimizer for pytOrch

neural-compressor

Intel® Neural Compressor (formerly known as Intel® Low Precision Optimization Tool), targeting to provide unified APIs for network compression technologies, such as low precision, sparsity, pruning, knowledge distillation, cross different deep learning frameworks to purse best inference performance.

neural-network-fpga

neural-networks-on-silicon

This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

nitta

NITTA - Tool for Hard Real-Time CGRA Processors

nn-size-reducing-papers

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

nocgen

NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers

nocrouter

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

npu-simulator

C++ Simulator for Neural Processing Unit