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arty-s7

Projects Created During 7 Ways to Leave Your Spartan 6 Challenge by element14

embedded-explorer

Config files for my GitHub profile.

exploring-c

Documenting the journey of exploring C Programming Language

exploring-systemc

This repository documents the journey of learning systemC

open-source-rtl-design

This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop

prjxray

Documenting the Xilinx 7-series bit-stream format.

rtl2gds-flow

Exploring RTL to GDS Flow in VLSI

scripting_essentials

stm32-code-in-asm

stm32-driver-development

stm32-using-hal

system-verilog-learning

System-Verilog Design Examples along with Complete Verification Environment

uart-implementation

Documents implementation of UART Controller using System-Verilog and Testing using Arty-S7 FPGA

uvm_learning

Documenting Journey of Exploring UVM

verilog-learning

This repo documents the learning of verilog HDL from various resources

vhdl-learning

This repository documents learing of VHDL from various resources

zynq7000-video-interfacing

This repository documents Interfacing HDMI and VGA with Pynq Z2 Board using Vivado block design and RTL.