- ๐ Hi, This is Hrishikesh
- ๐ VLSI Enthusiast
- ๐ฑ Working on RTL design for FPGAs
- ๐๏ธ Iโm looking to collaborate projects invloving RTL design using verilog
embedded-explorer / zynq7000-video-interfacing Goto Github PK
View Code? Open in Web Editor NEWThis repository documents Interfacing HDMI and VGA with Pynq Z2 Board using Vivado block design and RTL.