- ๐ Hi, This is Hrishikesh
- ๐ VLSI Enthusiast
- ๐ฑ Working on RTL design for FPGAs
- ๐๏ธ Iโm looking to collaborate projects invloving RTL design using verilog
embedded-explorer / open-source-rtl-design Goto Github PK
View Code? Open in Web Editor NEWThis repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop