esperantotech/boom-template

A template for building new projects/platforms using the BOOM core.

boom-template's Issues

Fails to clone riscv-qemu

It fails while initializing submodules.

`make output/rv64ui-p-simple.out` failed

Just a quick heads-up an an un-debugged observation (ie. a place-holder for a more useful report):

In my up-to-date Ubuntu 17.10 VM, all the steps in the README (appears to) work
for me up until the first test:

mkdir -p ./output
ln -fs /home/tommy/BOOM-local/boom-template/install/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple output/rv64ui-p-simple
cd /home/tommy/BOOM-local/boom-template/verisim && /home/tommy/BOOM-local/boom-template/verisim/simulator-boom.system-BoomConfig +max-cycles=10000000 +verbose output/rv64ui-p-simple 3>&1 1>&2 2>&3 | /home/tommy/BOOM-local/boom-template/install/bin/spike-dasm  > output/rv64ui-p-simple.out && [ $PIPESTATUS -eq 0 ]
/bin/sh: 1: [: -eq: unexpected operator
/home/tommy/BOOM-local/boom-template/Makefrag:52: recipe for target 'output/rv64ui-p-simple.out' failed

Given the contents of the .out file, I think the failure is bogus and the issue might be "$PIPESTATUS" whatever that's supposed to be.

Changes for bump BOOM in template branch and last rocket-chip master

ucb-bar/riscv-boom@9d34962ed9fbab33df630fae643058301bd944b9
chipsalliance/rocket-chip@61ef560

Diff list for boom:

diff --git a/src/main/scala/common/parameters.scala b/src/main/scala/common/parameters.scala
index f510be5..d3305bb 100644
--- a/src/main/scala/common/parameters.scala
+++ b/src/main/scala/common/parameters.scala
@@ -39,6 +39,7 @@ case class BoomCoreParams(
    enableBpdUSModeHistory: Boolean = false,
    enableBpdF2Redirect: Boolean = false,
    enableBpdF3Redirect: Boolean = true,
+   useAtomicsOnlyForIO: Boolean = false,
    btb: BTBsaParameters = BTBsaParameters(),
    tage: Option[TageParameters] = None,
    gshare: Option[GShareParameters] = None,
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
index 0fa6099..32bd505 100755
--- a/src/main/scala/exu/core.scala
+++ b/src/main/scala/exu/core.scala
@@ -275,7 +275,7 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
    if (fetchWidth == 1)
    {
       fetch_unit.io.imem.resp.bits.mask := UInt(1)
-      fetch_unit.io.imem.resp.bits.btb.bits.bridx := UInt(0)
+      fetch_unit.io.imem.resp.bits.btb.bridx := UInt(0)
    }
    fetch_unit.io.br_unit <> br_unit
    fetch_unit.io.tsc_reg           := debug_tsc_reg
diff --git a/src/main/scala/ifu/ScratchpadSlavePort.scala b/src/main/scala/ifu/ScratchpadSlavePort.scala
index fa1dd29..76339a9 100644
--- a/src/main/scala/ifu/ScratchpadSlavePort.scala
+++ b/src/main/scala/ifu/ScratchpadSlavePort.scala
@@ -123,7 +123,7 @@ trait CanHaveBoomScratchpad extends HasHellaCache with HasBoomICacheFrontend {
       val xbar = LazyModule(new TLXbar)
       xbar.node := slaveNode
       xbarPorts.foreach { case (port, bytes) =>
-        (Seq(port, TLFragmenter(bytes, cacheBlockBytes, earlyAck=true))
+        (Seq(port, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls))
           ++ (xBytes != bytes).option(TLWidthWidget(xBytes)))
           .foldRight(xbar.node:TLOutwardNode)(_ := _)
       }
diff --git a/src/main/scala/ifu/fetch.scala b/src/main/scala/ifu/fetch.scala
index 156b1db..6e751a3 100644
--- a/src/main/scala/ifu/fetch.scala
+++ b/src/main/scala/ifu/fetch.scala
@@ -493,8 +493,6 @@ class FetchUnit(fetch_width: Int)(implicit p: Parameters) extends BoomModule()(p
    // **** Assertions ****
    //-------------------------------------------------------------
 
-   assert (!(io.imem.resp.bits.btb.valid), "[bpd_pipeline] BTB predicted, but it's been disabled.")
-
    // check if enqueue'd PC is a target of the previous valid enqueue'd PC.
 
    // clear checking if misprediction/flush/etc.
@@ -625,11 +623,10 @@ class FetchUnit(fetch_width: Int)(implicit p: Parameters) extends BoomModule()(p
             )
       }
 
-      printf("----BrPred2:(%c,%c,%d) [btbtarg: 0x%x]\n"
-         , Mux(io.imem.resp.bits.btb.valid, Str("H"), Str("-"))
-         , Mux(io.imem.resp.bits.btb.bits.taken, Str("T"), Str("-"))
-         , io.imem.resp.bits.btb.bits.bridx
-         , io.imem.resp.bits.btb.bits.target(19,0)
+      printf("----BrPred2:(%c,%d) [btbtarg: 0x%x]\n"
+         , Mux(io.imem.resp.bits.btb.taken, Str("T"), Str("-"))
+         , io.imem.resp.bits.btb.bridx
+         , io.imem.resp.bits.btb.target(19,0)
          )
 
       // Fetch Stage 3

How to merge this into fpga-zynq repo

I want to synthesize rocket-chip with BOOM cores on zedboard, but I can't find how to do that.

Build fails due to Chisel3

Hello
I followed installation instructions and tried to build a Small config with:
make run CONFIG=SmallBoomConfig. I use Ubuntu 16.04, javac 1.8.0_181 and the latest rocket-chip

[info] Compiling 242 Scala sources to /home/bku/work/cores/bar/boom-template/rocket-chip/target/scala-2.12/classes ...
[error] /home/bku/work/cores/bar/boom-template/rocket-chip/src/main/scala/jtag/JtagStateMachine.scala:88:22: exception during macro expansion:
[error] java.lang.NoSuchMethodError: scala.collection.immutable.$colon$colon.tl$1()Lscala/collection/immutable/List;
[error] at chisel3.util.switch$$anonfun$2$$anon$2.unapply(Conditional.scala:100)
[error] at chisel3.util.switch$$anonfun$2.apply(Conditional.scala:100)
[error] at chisel3.util.switch$$anonfun$2.apply(Conditional.scala:97)
[error] at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:122)
[error] at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:118)
[error] at scala.collection.immutable.List.foldLeft(List.scala:86)
[error] at chisel3.util.switch$.impl(Conditional.scala:97)
[error] switch (currState) {
[error] ^
[error] /home/bku/work/cores/bar/boom-template/rocket-chip/src/main/scala/rocket/PTW.scala:242:18: exception during macro expansion:
[error] java.lang.NoSuchMethodError: scala.collection.immutable.$colon$colon.tl$1()Lscala/collection/immutable/List;
[error] at chisel3.util.switch$$anonfun$2$$anon$2.unapply(Conditional.scala:100)
[error] at chisel3.util.switch$$anonfun$2.apply(Conditional.scala:100)
[error] at chisel3.util.switch$$anonfun$2.apply(Conditional.scala:97)
[error] at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:122)
[error] at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:118)
[error] at scala.collection.immutable.List.foldLeft(List.scala:86)
[error] at chisel3.util.switch$.impl(Conditional.scala:97)
[error] switch (state) {

make verilog

I was wondering which are the differences in the generated src files in doing:

1:
cd verisim
make

2:
cd vsim
make verilog

I noticed that the two src verilog files, in the respectively "generated-src" folders, differ.

MegaBoomConfig & MediumBoomConfig Build fails due to require(nWays == 4) in src/main/scala/bpu/dense-btb.scala

I got the master branch at 7208cba and followed the step to build, all the way to verisim except for disabling the build for riscv-openocd.

build-rv64g.sh
#build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --disable-werror

$ cd verisim
$ make
$ make CONFIG=SmallBoomConfig

Above, both successful.

$ make CONFIG=MediumBoomConfig
$ make CONFIG=MegaBoomConfig

Both fail at dense-btb.scala:100

[error] Caused by: java.lang.IllegalArgumentException: requirement failed
[error] at scala.Predef$.require(Predef.scala:264)
[error] at boom.bpu.DenseBTB.(dense-btb.scala:100)
[error] at boom.bpu.BoomBTB$.$anonfun$apply$2(btb.scala:199)
[error] at chisel3.core.Module$.do_apply(Module.scala:49)

src/main/scala/bpu/dense-btb.scala: 100
require(nWays == 4)

Both configs have nWays=2 for BoomBTBParameters.

If I comment out this line then MediumBoomConfig can be built successfully. MegaBoomConfig will not report this error but stuck at a different place:

[error] Caused by: java.lang.IllegalArgumentException: requirement failed: Handling aliases in the ICache is buggy.
[error] at scala.Predef$.require(Predef.scala:277)
[error] at boom.common.HasBoomCoreParameters.$init$(parameters.scala:165)
[error] at boom.common.BoomBundle.(types.scala:12)

Changes to sync with freechipsproject/rocket-chip@5155eb6

Here is changes to synchronize with current chipsalliance/rocket-chip@5155eb6
master branch.

diff --git a/src/main/scala/common/tile.scala b/src/main/scala/common/tile.scala
index 361851b..59df15b 100644
--- a/src/main/scala/common/tile.scala
+++ b/src/main/scala/common/tile.scala
@@ -24,6 +24,7 @@ case class BoomTileParams(
     hcfOnUncorrectable: Boolean = false,
     name: Option[String] = Some("tile"),
     hartid: Int = 0,
+    blockerCtrlAddr: Option[BigInt] = None,
     boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
     ) extends TileParams {
   require(icache.isDefined)
diff --git a/src/main/scala/ifu/ScratchpadSlavePort.scala b/src/main/scala/ifu/ScratchpadSlavePort.scala
index 76339a9..02fe0fc 100644
--- a/src/main/scala/ifu/ScratchpadSlavePort.scala
+++ b/src/main/scala/ifu/ScratchpadSlavePort.scala
@@ -6,7 +6,8 @@ import Chisel._
 import Chisel.ImplicitConversions._
 
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.coreplex.CacheBlockBytes
+import freechips.rocketchip.coreplex.{CacheBlockBytes, SystemBusKey}
+import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
@@ -99,9 +100,10 @@ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics:
 trait CanHaveBoomScratchpad extends HasHellaCache with HasBoomICacheFrontend {
   val module: CanHaveBoomScratchpadModule
   val cacheBlockBytes = p(CacheBlockBytes)
+  val masterPortBeatBytes = p(SystemBusKey).beatBytes
 
   val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s =>
-    LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics)))
+    LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)))
   }
 
   val intOutputNode = tileParams.core.tileControlAddr.map(dummy => IntIdentityNode())
@@ -111,13 +113,21 @@ trait CanHaveBoomScratchpad extends HasHellaCache with HasBoomICacheFrontend {
     beu
   }
 
+  val tile_master_blocker =
+    tileParams.blockerCtrlAddr
+      .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true))
+      .map(bp => LazyModule(new BasicBusBlocker(bp)))
+
+  masterNode := tile_master_blocker.map { _.node := tileBus.node } getOrElse { tileBus.node }
+
   // connect any combination of ITIM, DTIM, and BusErrorUnit
   val slaveNode = TLIdentityNode()
   DisableMonitors { implicit p =>
     val xbarPorts =
       scratch.map(lm => (lm.node, xBytes)) ++
       busErrorUnit.map(lm => (lm.node, xBytes)) ++
-      tileParams.icache.flatMap(icache => icache.itimAddr.map(a => (frontend.slaveNode, tileParams.core.fetchBytes)))
+      tileParams.icache.flatMap(icache => icache.itimAddr.map(a => (frontend.slaveNode, tileParams.core.fetchBytes))) ++
+      tile_master_blocker.map( lm => (lm.controlNode, xBytes))
 
     if (xbarPorts.nonEmpty) {
       val xbar = LazyModule(new TLXbar)

And may I ask you to add this to commit?

diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala
index f108a69..e2d31a4 100644
--- a/src/main/scala/system/Configs.scala
+++ b/src/main/scala/system/Configs.scala
@@ -24,6 +24,7 @@ class BoomConfig extends Config(new DefaultBoomConfig ++ new WithNBoomCores(1) +
 class SmallBoomConfig extends Config(new WithSmallBooms ++ new DefaultBoomConfig ++ new WithNBoomCores(1) ++ new WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig)
 class MediumBoomConfig extends Config(new WithMediumBooms ++ new DefaultBoomConfig ++ new WithNBoomCores(1) ++ new WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig)
 class MegaBoomConfig extends Config(new WithMegaBooms ++ new DefaultBoomConfig ++ new WithNBoomCores(1) ++ new WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig)
+class jtagMegaBoomConfig extends Config(new WithMegaBooms ++ new DefaultBoomConfig ++ new WithNBoomCores(1) ++ new WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig ++ new WithJtagDTM)

It seems to me there is no need to produce forks for the sake of adding a configuration that can be useful to everyone. Maybe jtagMediumBoomConfig and jtagSmallBoomConfig should be done too.

vcd file

I am trying to debug a design.
I am using this to get the vpd file and change it to vcd file using vpd2vcd.
/mada/users/nferdous/boom-template/verisim/simulator-boom.system-BoomConfig-debug +max-cycles=10000000 +verbose -voutput/dhrystone.riscv.vpd output/dhrystone.riscv 3>&1 1>&2 2>&3 | /mada/software/riscv/bin/spike-dasm > output/dhrystone.riscv.out && [ $PIPESTATUS -eq 0 ]
However, The vpdfile is not converted to vcd (although the vpd in the rocket chip is working good). Please let me know how I can get the vcd file instead of vpd.

Error during cloning boom

Using master branch and a fresh clone, we get the following error:

$ ./scripts/init-submodules.sh
Submodule 'boom' (https://github.com/ucb-bar/riscv-boom.git) registered for path 'boom'
Submodule 'rocket-chip' (https://github.com/ucb-bar/rocket-chip.git) registered for path 'roc
ket-chip'
Submodule 'torture' (https://github.com/ucb-bar/riscv-torture.git) registered for path 'tortu
re'
Cloning into 'boom'...
remote: Enumerating objects: 9625, done.
remote: Total 9625 (delta 0), reused 0 (delta 0), pack-reused 9625
Receiving objects: 100% (9625/9625), 7.79 MiB | 0 bytes/s, done.
Resolving deltas: 100% (5957/5957), done.
Checking connectivity... done.
fatal: reference is not a tree: d0dad4e3250669fd6ca0ae5e888dbdd4f620d845