Comments (1)
Additional Verilog sources, like RoccBlackBox.v, are supposed to be added to Vivado project file, not to system-vc707.v, which is generated from Chisel. The project file is created by vivado.tcl script. You can modify the script to include more Verilog files.
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Related Issues (20)
- Makefile:240: workspace/rocket64b2/system.dts] Error 1 HOT 2
- Question about the bootrom generation HOT 1
- CAN Digilent Pmod IP or Vivado IP? HOT 9
- Bare-metal application with custom Peripheral HOT 10
- What is the correct workflow for 'modding the design' (adding new peripheral) HOT 3
- cannot read boot.elf : File not found HOT 1
- Problems when connecting the Rocketchip core with JTAG interface using BSCANE2 and bscan2jtag module HOT 2
- Understanding the role of co-simulation HOT 4
- Problems when recompiling the bootrom with a new maskrom_mem address range and a new dtb address HOT 1
- Problems when recompiling the bootrom with a new maskrom_mem address range and a new dtb address HOT 1
- How to use RGMII instead of GMII for the ethernet on BOARD=kc705? HOT 4
- How to add more packages/dependencies into riscv-linux HOT 1
- Some questions about Booting Linux with QEMU HOT 1
- Question about RocketChip MEM_AXI4 to DDR memory HOT 6
- Question about running a program in vivado simulation HOT 1
- Kernel boot fail on Arty 100T board HOT 3
- Error in Makefile for command: make CONFIG=rocket64b2 BOARD=nexys-video vivado-gui HOT 4
- VCU118 boot failed with v3.6.0
- How do I write the device-tree binding to bring up PCI in Linux
- Large size of memory HOT 2
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