eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

vivado-risc-v's Issues

What are the required steps to port to Alveo U2xx cards

Hi,

I would like to build larger systems and have access to Alveo cards. Can you please tell us what we'd need to do to port to Alveo U2xx? I am particularly interested in connecting to HBM on U280 to benchmark improvements.

Thank you for this excellent repo. I hope it gets folded back in to chipyard proper as "F1" is NOT FPGA support. Running a simulation is not the same as building the code for and executing on FPGAs. There are many places I've seen in the docs where that seems to get confused. ;)

Cheers,

Glenn

rocketchip to vcu118

I want to migrate to vcu118 and run Linux. Which project should I modify from, vcu1525 or vc707, but vcu1525 has no SD card module,thank you

fan is not active

How can I add fan support for vc707.
I notice that the board is getting warm and I am worried that this will break it.

Debug with Vitis

Hi,

I'm new in RISCV FPGA Design, so sorry if I am a bit of a noob here.
My question is how can I debug with Vitis ? When I export Hardware the xsa file is created.
After that I launch Vitis and create a new application project and select the xsa file and it is asked to choose a processor for an application project, but there is no existing target processor.
So my question is how to debug with the RISCV with Vitis.

Thanks very much

Question for Boom version

Hi, can I use boom v2 or boom v1 code for this project and run it on fpga? Thank you so much.

Unspecified I/O standard and Unconstrained Logic Port error

Hi, when I tried to generate the bitstream using this command "make CONFIG=rocket64b1 BOARD=vc707 bitstream",I used vivado2019.1 to run the project firstly，and find there is no corresponding vivado tcl file, so I renamed the 2020.1 version tcl file as 2019.1.tcl to run through the makefile. And later I encountered this error:

And In the vivado project, the error shows:

So I installed the vivado of 2021.1 and delete the vivado project file( all the files in directory workspace/rocket64b1 ). And I try to run again this command "make CONFIG=rocket64b1 BOARD=vc707 bitstream".But It still has the same error as above.
What does these error mean and how to fix them? And I am confused about if I didn't delete some file(generated by 2019.1 vivado) completely?
Thanks a lot!

Why ssh work only in the same ip domain

Hi, I know nothing about computer networks or ethernet. But I find that after the board connect to the internet and it has an IP address, and when the local machine connecting to it using ssh, the local machine must have the same the first three IP address as the board. Such as when the IP address of the board is 192.168.0.62, then the local machine must have an IP address like 192.168.0.xx, otherwise, it simply cannot connect to the board. Furthermore, this situation is the same for using the tvm runtime with rpc(Remote Procedure Call).
This situation causes a little inconvenience in practice. So what is the principle behind the board connecting to the internet and is there any method to remove this "IP same" constrain?

Thanks a lot~

Can I build's two boom cores in a project?

Hello, which FPGA board can I run a two-core Boom Medium core on, please?

Failed to start device monitor after adding L2

Hello. For some reason, I want to add an accelerator gemmini to the rocket in this repo. So I added some codes to scala file src/main/scala/rocket.scala as follows:

class Rocket64s1ori extends Config(
  new WithNBreakpoints(8) ++
  new WithCoreFreq(100000000) ++
  new WithNBigCores(1) ++
  new WithCoherentBusTopology ++
  new RocketBaseConfig)

class Rocket64s1 extends Config(
  new WithL2TLBs(1024) ++
  new gemmini.DefaultGemminiConfig ++ 
  new WithInclusiveCache ++
  new WithNBreakpoints(8) ++
  new WithCoreFreq(100000000) ++
  new WithNBigCores(1) ++
  new WithCoherentBusTopology ++
  new RocketBaseConfig)

I have modified the makefile build.sbt and added the needed repos.
The config Rocket64s1ori works well and can boot linux while the config Rocket64s1 encountered some problems during booting linux:

...
[    5.294722] workingset: timestamp_bits=62 max_order=17 bucket_order=0
[    5.465488] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    5.491532] NFS: Registering the id_resolver key type
[    5.495954] Key type id_resolver registered
[    5.499776] Key type id_legacy registered
[    5.503888] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    5.513648] 9p: Installing v9fs 9p2000 file system support
[    5.524482] NET: Registered protocol family 38
[    5.528554] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
[    5.535334] io scheduler mq-deadline registered
[    5.539774] io scheduler kyber registered
[    6.573720] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    6.599500] uartlite 60010000.uartlite: IRQ index 0 not found
[    6.612568] [drm] radeon kernel modesetting enabled.
[    6.795148] loop: module loaded
[    6.815460] libphy: Fixed MDIO Bus: probed
[    6.834584] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
[    6.839440] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[    6.847892] riscv-axi-eth 60020000.eth0: IRQ index 0 not found
[    6.855678] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    6.861440] ehci-pci: EHCI PCI platform driver
[    6.866272] ehci-platform: EHCI generic platform driver
[    6.872028] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    6.877898] ohci-pci: OHCI PCI platform driver
[    6.882458] ohci-platform: OHCI generic platform driver
[    6.894178] usbcore: registered new interface driver uas
[    6.899564] usbcore: registered new interface driver usb-storage
[    6.908032] mousedev: PS/2 mouse device common for all mice
[    6.972886] usbcore: registered new interface driver usbhid
[    6.977518] usbhid: USB HID core driver
[    6.999060] NET: Registered protocol family 10
[    7.017808] Segment Routing with IPv6
[    7.021886] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    7.038474] NET: Registered protocol family 17
[    7.046152] 9pnet: Installing 9P2000 support
[    7.050402] Key type dns_resolver registered
[    7.070672] Warning: unable to open an initial console.
[    7.082130] Freeing unused kernel memory: 232K
[    7.094576] Run /init as init process
[    7.108906] mmc0: host does not support reading read-only switch, assuming write-enable
[    7.128014] mmc0: new high speed SDXC card at address 0001
[    7.178174] mmcblk0: mmc0:0001 ED4QT 119 GiB
[    7.229910]  mmcblk0: p1 p2
[    8.060446] systemd-udevd[55]: Starting version 245.5-1
[    8.097762] systemd-udevd[56]: Failed to start device monitor: Operation not permitted

The new system.dts adds a piece of code about cache-controller

...
	L11: memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};
	L15: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "freechips,rocketchip-vivado-soc", "simple-bus";
		ranges;
		L2: cache-controller@2010000 {
			cache-block-size = <64>;
			cache-level = <2>;
			cache-sets = <1024>;
			cache-size = <524288>;
			cache-unified;
			compatible = "sifive,inclusivecache0", "cache";
			next-level-cache = <&L11>;
			reg = <0x2010000 0x1000>;
			reg-names = "control";
			sifive,mshr-count = <12>;
		};
		L4: clint@2000000 {
			compatible = "riscv,clint0";
			interrupts-extended = <&L7 3 &L7 7>;
			reg = <0x2000000 0x10000>;
			reg-names = "control";
		};
		L5: debug-controller@0 {
			compatible = "sifive,debug-013", "riscv,debug-013";
			debug-attach = "dmi";
			interrupts-extended = <&L7 65535>;
			reg = <0x0 0x1000>;
			reg-names = "control";
		};
...

Where might the problem be and how can I solve it

Execute the command "make update-submodules" failed.....Someone has the same problems?

Connection timed out

Hi,

I got the following error messages when I run make update-submodules.

fatal: clone of 'git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git' into submodule path '/home/ams/Documents/Pytorch-dir/ACU-4/Docker/vivado-risc-v/linux-stable' failed
Failed to clone 'linux-stable' a second time, aborting
make: *** [Makefile:11: update-submodules] Error 1

Do you know the reason for that error?

Thanks and best regards,
Ammad

16 or more RISC-V cores

If I want to build 16 or more RISC-V cores, which FPGA board is suitable for this task ?
I have an used new VCU129-PP FPGA board, is it ok ? Many thanks.

testing benchmarks in this debian OS has no outputs

There is no output when running the test program in the system after startup. I don't know why. The test procedures include dhrystone and coremark. Could you give me some suggestions, thanks.

Porting to KC705 FPGA board

Thank you for creating the project. The bitstream generation flow was extremely convenient for mapping a RISC-V SoC to FPGA.

I was wondering how much effort would be needed to remap this flow (or at least the rocket64b2gem config) onto a Xilinx KC705 board.

I suppose I should use genesys2 as a base config and make some modifications to adapt to KC705 as they have the same FPGA chip (xc7k325tffg900-2). I understand that the .xdc constraint files under /board/genesys2 need to be changed to that of the KC705 board. Aside from that can you please guide me on what other factors would I have to consider?

Thank you

makefile boom source directory

CHISEL_SRC := $(foreach path, src/main rocket-chip/src/main riscv-boom/src/main, $(shell test -d $(path) && find $(path) -iname "*.scala"))
Do I need to modify "riscv-boom/src/main" to "generators/riscv-boom/src/main"?
Thank you.

Problems with Rocket simulation

Hi,

I'm having trouble getting this to work with my FPGA board.

I'm using your project because of the nice vhdl-wrapper to interface it with vivado block-design,
however, I'm trying to debug my custom bootrom and I'm having some trouble.

First of all, no matter the RocketChip configuration, if I try to debug it using vivado,
the PC and other important signals get stuck at "X".

However, If I try a BOOM configuration, the bootrom seems to execute fine, It seems like the MEM port works,
but I can't get any read/write on the IO_PORT.

Is there any bug related to this behaviour?

My simulation is quite simple, a testbench with a reset and a clock.
While the block design has connected the mem and io to a bram.

If you could give me some guidelines to get this to work I would be extremely happy.

Also, I saw that you check for "rocket64" string in the configuration in order to decide the gcc-toolchain for the bootrom.
I would suggest to make it caps-unaware since writing "Rocket64x1" on CONFIG will create the processor, but with a 32bit bootrom attached.

Thaks for your time!

Bootrom on PCIe cards

How can I boot linux and run programs on PCIe-based accelerator cards, like Alveo U200 and VCU1525?
And if possible, can I build a larger amount of cores on them?
I changed the amount of cores to 50 it failed to run synthesis

OpenOCD not working on Nexys Video

When I try to run the openocd, i face the following error:

tirumal@ACER-SWIFT-3:~$ sudo $(which openocd) -f ./openocd.cfg 
Open On-Chip Debugger 0.11.0-rc2+dev-01538-gd57ab0b63 (2021-03-01-19:50)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter speed' not 'adapter_khz'
DEPRECATED! use 'adapter driver' not 'interface'
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : Nested Tap based Bscan Tunnel Selected
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Error: no device found
Error: unable to open ftdi device with vid 0403, pid 6014, description '*', serial '*' at bus location '*'

My openocd.cfg file:

  adapter_khz 20000
  interface ftdi
  ftdi_vid_pid 0x0403 0x6014
  ftdi_layout_init 0x00e8 0x60eb
  ftdi_tdo_sample_edge falling
  reset_config none
  set _CHIPNAME riscv
  jtag newtap $_CHIPNAME cpu -irlen 6
  set _TARGETNAME $_CHIPNAME.cpu
  target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
  $_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
  riscv use_bscan_tunnel 5

Running Gemmini on Nexys4-DDR

hi, I'm trying to run a Gemmini on Nexys-4DDR(Nexys A7-100T)，first I run the following command ：make CONFIG=rocket64b1gem BOARD=nexys-a7-100t bitstream, then it occurred errors：
[error] (run-main-0) java.lang.Exception: Unable to find part "Vivado.Rocket64b1gem" from "ArrayBuffer(Vivado.Rocket64b1gem)", did you misspell it or specify the wrong package path?
secondly, I used the parameter rocket64b2gem，it occurred：
ERROR: [DRC UTLZ-1] Resource utilization: LUT as Logic over-utilized in Top Level Design (This design requires more LUT as Logic cells than are available in the target device. This design requires 136675 of such cell types but only 63400 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
I am wondering if it is possible to run one rocket core with one Gemmini part on my board? Thanks!

Issue with UART

I connected UART controller to another riscv core in the same way it is connected to rocket core. I am using uart controller for read and write into an external device from user space. I used fpga-axi-uart.c as KMD. I am trying a simple loop back application on it. I attached an led to the TxD of uart, it is not blinking when I am writing into the registers instead it is continuously staying high whether I write anything or not. stty -F /dev/ttyAU0 shows that data is written but it is showing that there is no data in RxD even though I connected TxD and RxD. I also connected RTS to CTS. I am not getting what is the problem here, please help me.

No UART output for VC707

I have programmed the 8 cores bit file to VC707 FPGA board with programmed SD card. There is no output from the UART. However, I have done the same thing using Genesys 2 FPGA board (4 cores bit file). Everything is ok. Linux can be booted. So, how can I fix the problems on VC707 FPGA ? Thanks a lot.

Stuck on sfdisk step of mk-sd-image script

Hi Eugene,

first of all congratulations on the massive work done in this repository. I was really glad when you posted this repo in the thread I had opened inside Xilinx's forum about RISC-V implementations.

I have a Genesys II board and I finally have time to start working with the designs provided in this repo too.
Unfortunately my current set-up is on a Centos 7 machine.
I believe I have solved all of the dependencies with respect to successfully generating a memory configuration file (genesys2-riscv.mcs) and a bitstream (riscv_wrapper.bit) for my board.

But I am having problems with generating and copying the Linux image on the SD card. I am running the ./mk-sd-card command to create the image on the SD card. I am facing a problem with the following lines in the mk-sd-image file:

sudo sfdisk --no-tell-kernel ${SD_LOOP} <<-__EOF__
1M,400M,0xE,*
,,,-
__EOF__

The script aborts with the following output:

SD image device: 
sfdisk: unrecognized option '--no-tell-kernel'

Searching about this, it has to do with fdisk being an older version than the one you are using to build inside Ubuntu.
The version inside Centos 7 doesn't support the --no-tell-kernel option.

If I try to omit the --no-tell-kernel option from the command, the script aborts with the following:

SD image device: 

Usage:
 sfdisk [options] <device> [...]

I have seen in #23 , that I should be getting at this point probably something like the following:

SD image device: /dev/loop#

So for whatever reason, the lines 38-64 do not seem to work in Centos, in terms of creating (?) the /dev/loop# :

mount -l | grep `pwd`/ | while IFS=' ' read -ra LINE ; do
  sudo umount ${LINE[0]}
done
losetup -a | grep `pwd`/ | while IFS=':' read -ra LINE ; do
  sudo losetup -d ${LINE[0]}
done
losetup -a | grep `pwd`/ | while IFS=':' read -ra LINE ; do
  echo "Cannot detach ${LINE[*]}"
  exit 1
done

rm -f $SD_IMG
dd if=/dev/zero of=$SD_IMG bs=1M count=$SD_SIZE
sudo losetup -f $SD_IMG

SD_LOOP=$(
losetup -a | grep `pwd`/ | while IFS=':' read -ra LINE ; do
  echo ${LINE[0]}
done
)

echo "SD image device: ${SD_LOOP}"

##sudo sfdisk --no-tell-kernel ${SD_LOOP} <<-__EOF__
sudo sfdisk ${SD_LOOP} <<-__EOF__
1M,400M,0xE,*
,,,-
__EOF__

When I am running the command losetup -a, I get the following output:

[user1@nassos2 vivado-risc-v]$ losetup -a
/dev/loop0: []: (/path/xilinx_riscv/vivado-risc-v/debian-riscv64/debian-riscv64.sd.img (deleted))
/dev/loop1: []: (/path/xilinx_riscv/vivado-risc-v/debian-riscv64/debian-riscv64.sd.img (deleted))
/dev/loop2: []: (/path/xilinx_riscv/vivado-risc-v/debian-riscv64/debian-riscv64.sd.img)

I am using CentOS Linux release 7.9.2009 (Core).

Any ideas on how to overcome this issue and be able to create the image in the SD card, would be really helpful!

Thank you in advance for your response and time!
Feel free to ask if more information are needed.

Kind regards,
Nassos

P.S. I tried installing a newer version of the fdisk in Centos, but with no success due to several dependency issues.

Can

JDK and sbt version error

Hi,

I have some struggles building the fpga bitstream using Vitis 2021.1.

When I try make CONFIG=rocket64b2 BOARD=nexys-video bitstream using jdk11 the following error occured:

Error: LinkageError occurred while loading main class net.largest.riscv.vhdl.Main
java.lang.UnsupportedClassVersionError: net/largest/riscv/vhdl/Main has been compiled by a more recent version of the Java Runtime (class file version 58.0), this version of the Java Runtime only recognizes class file versions up to 55.0
make: *** [Makefile:191: workspace/rocket64b2/rocket.vhdl] Error 1

I changed the jdk version to jdk14 and got a different error:

[info] compiling 27 Scala sources to /localtemp2/reinhardt/second_try/vivado-risc-v/rocket-chip/hardfloat/target/scala-2.12/classes ...
[error] ## Exception when compiling 27 sources to /localtemp2/reinhardt/second_try/vivado-risc-v/rocket-chip/hardfloat/target/scala-2.12/classes
[error] java.io.IOError: java.lang.RuntimeException: /packages cannot be represented as URI
[error] java.base/jdk.internal.jrtfs.JrtPath.toUri(JrtPath.java:176)
[error] scala.tools.nsc.classpath.JrtClassPath.asURLs(DirectoryClassPath.scala:213)
[error] scala.tools.nsc.classpath.AggregateClassPath.$anonfun$asURLs$1(AggregateClassPath.scala:64)
[error] scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:244)
[error] scala.collection.Iterator.foreach(Iterator.scala:941)
[error] scala.collection.Iterator.foreach$(Iterator.scala:941)
[error] scala.collection.AbstractIterator.foreach(Iterator.scala:1429)
[error] scala.collection.IterableLike.foreach(IterableLike.scala:74)
[error] scala.collection.IterableLike.foreach$(IterableLike.scala:73)
[error] scala.collection.AbstractIterable.foreach(Iterable.scala:56)
[error] scala.collection.TraversableLike.flatMap(TraversableLike.scala:244)
[error] scala.collection.TraversableLike.flatMap$(TraversableLike.scala:241)
[error] scala.collection.AbstractTraversable.flatMap(Traversable.scala:108)
[error] scala.tools.nsc.classpath.AggregateClassPath.asURLs(AggregateClassPath.scala:64)
[error] scala.tools.nsc.typechecker.Macros.findMacroClassLoader(Macros.scala:78)
[error] scala.tools.nsc.typechecker.Macros.findMacroClassLoader$(Macros.scala:77)
[error] scala.tools.nsc.Global$$anon$4.findMacroClassLoader(Global.scala:477)
[error] scala.reflect.macros.runtime.MacroRuntimes.$anonfun$defaultMacroClassloaderCache$2(MacroRuntimes.scala:68)
[error] scala.reflect.internal.SymbolTable$perRunCaches$$anon$2.apply(SymbolTable.scala:477)
[error] scala.reflect.macros.runtime.MacroRuntimes.defaultMacroClassloader(MacroRuntimes.scala:70)
[error] scala.reflect.macros.runtime.MacroRuntimes.defaultMacroClassloader$(MacroRuntimes.scala:70)
[error] scala.tools.nsc.Global$$anon$4.defaultMacroClassloader(Global.scala:477)
[error] scala.reflect.macros.runtime.MacroRuntimes$MacroRuntimeResolver.resolveRuntime(MacroRuntimes.scala:88)
[error] scala.reflect.macros.runtime.MacroRuntimes.$anonfun$standardMacroRuntime$3(MacroRuntimes.scala:50)
[error] scala.collection.mutable.MapLike.getOrElseUpdate(MapLike.scala:209)
[error] scala.collection.mutable.MapLike.getOrElseUpdate$(MapLike.scala:206)
[error] scala.collection.mutable.AbstractMap.getOrElseUpdate(Map.scala:82)
[error] scala.reflect.macros.runtime.MacroRuntimes.standardMacroRuntime(MacroRuntimes.scala:50)
[error] scala.reflect.macros.runtime.MacroRuntimes.standardMacroRuntime$(MacroRuntimes.scala:43)
[error] scala.tools.nsc.Global$$anon$4.standardMacroRuntime(Global.scala:477)
[error] scala.tools.nsc.typechecker.AnalyzerPlugins$$anon$14.default(AnalyzerPlugins.scala:455)
[error] scala.tools.nsc.typechecker.AnalyzerPlugins$$anon$14.default(AnalyzerPlugins.scala:452)
[error] scala.tools.nsc.typechecker.AnalyzerPlugins.invoke(AnalyzerPlugins.scala:414)
[error] scala.tools.nsc.typechecker.AnalyzerPlugins.pluginsMacroRuntime(AnalyzerPlugins.scala:452)
[error] scala.tools.nsc.typechecker.AnalyzerPlugins.pluginsMacroRuntime$(AnalyzerPlugins.scala:452)
[error] scala.tools.nsc.Global$$anon$4.pluginsMacroRuntime(Global.scala:477)
[error] scala.reflect.macros.runtime.MacroRuntimes.macroRuntime(MacroRuntimes.scala:37)
[error] scala.reflect.macros.runtime.MacroRuntimes.macroRuntime$(MacroRuntimes.scala:37)
[error] scala.tools.nsc.Global$$anon$4.macroRuntime(Global.scala:477)
[error] scala.tools.nsc.typechecker.Macros$MacroExpander.$anonfun$expand$1(Macros.scala:631)
[error] scala.tools.nsc.Global.withInfoLevel(Global.scala:227)
[error] scala.tools.nsc.typechecker.Macros$MacroExpander.expand(Macros.scala:625)
[error] scala.tools.nsc.typechecker.Macros$MacroExpander.apply(Macros.scala:612)
[error] scala.tools.nsc.typechecker.Macros.standardMacroExpand(Macros.scala:787)
[error] scala.tools.nsc.typechecker.Macros.standardMacroExpand$(Macros.scala:785)
[error] scala.tools.nsc.Global$$anon$4.standardMacroExpand(Global.scala:477)
[error] scala.tools.nsc.typechecker.AnalyzerPlugins$$anon$12.default(AnalyzerPlugins.scala:439)
[error] scala.tools.nsc.typechecker.AnalyzerPlugins$$anon$12.default(AnalyzerPlugins.scala:436)
[error] scala.tools.nsc.typechecker.AnalyzerPlugins.invoke(AnalyzerPlugins.scala:414)
[error] scala.tools.nsc.typechecker.AnalyzerPlugins.pluginsMacroExpand(AnalyzerPlugins.scala:436)
[error] scala.tools.nsc.typechecker.AnalyzerPlugins.pluginsMacroExpand$(AnalyzerPlugins.scala:436)
[error] scala.tools.nsc.Global$$anon$4.pluginsMacroExpand(Global.scala:477)
[error] scala.tools.nsc.typechecker.Macros.macroExpand(Macros.scala:776)
[error] scala.tools.nsc.typechecker.Macros.macroExpand$(Macros.scala:769)
[error] scala.tools.nsc.Global$$anon$4.macroExpand(Global.scala:477)
[error] scala.tools.nsc.typechecker.Typers$Typer.vanillaAdapt$1(Typers.scala:1183)
[error] scala.tools.nsc.typechecker.Typers$Typer.adapt(Typers.scala:1243)
[error] scala.tools.nsc.typechecker.Typers$Typer.typed(Typers.scala:5740)
[error] scala.tools.nsc.typechecker.Typers$Typer.typedSelectOrSuperCall$1(Typers.scala:5810)
[error] scala.tools.nsc.typechecker.Typers$Typer.typed1(Typers.scala:5681)
[error] scala.tools.nsc.typechecker.Typers$Typer.typed(Typers.scala:5726)
[error] scala.tools.nsc.typechecker.Typers$Typer.$anonfun$typed1$38(Typers.scala:4855)
[error] scala.tools.nsc.typechecker.Typers$Typer.silent(Typers.scala:713)
[error] scala.tools.nsc.typechecker.Typers$Typer.normalTypedApply$1(Typers.scala:4857)
[error] scala.tools.nsc.typechecker.Typers$Typer.typedApply$1(Typers.scala:4885)
[error] scala.tools.nsc.typechecker.Typers$Typer.typed1(Typers.scala:5680)
[error] scala.tools.nsc.typechecker.Typers$Typer.typed(Typers.scala:5726)
[error] scala.tools.nsc.typechecker.Typers$Typer.computeType(Typers.scala:5801)
[error] scala.tools.nsc.typechecker.Namers$Namer.assignTypeToTree(Namers.scala:1090)
[error] scala.tools.nsc.typechecker.Namers$Namer.valDefSig(Namers.scala:1708)
[error] scala.tools.nsc.typechecker.Namers$Namer.memberSig(Namers.scala:1877)
[error] scala.tools.nsc.typechecker.Namers$Namer.typeSig(Namers.scala:1842)
[error] scala.tools.nsc.typechecker.Namers$Namer$ValTypeCompleter.completeImpl(Namers.scala:921)
[error] scala.tools.nsc.typechecker.Namers$LockingTypeCompleter.complete(Namers.scala:2039)
[error] scala.tools.nsc.typechecker.Namers$LockingTypeCompleter.complete$(Namers.scala:2037)
[error] scala.tools.nsc.typechecker.Namers$TypeCompleterBase.complete(Namers.scala:2032)
[error] scala.reflect.internal.Symbols$Symbol.info(Symbols.scala:1542)
[error] scala.reflect.internal.Symbols$Symbol.initialize(Symbols.scala:1690)
[error] scala.tools.nsc.typechecker.Typers$Typer.typed1(Typers.scala:5349)
[error] scala.tools.nsc.typechecker.Typers$Typer.typed(Typers.scala:5726)
[error] scala.tools.nsc.typechecker.Typers$Typer.typedStat$1(Typers.scala:5790)
[error] scala.tools.nsc.typechecker.Typers$Typer.$anonfun$typedStats$10(Typers.scala:3373)
[error] scala.tools.nsc.typechecker.Typers$Typer.typedStats(Typers.scala:3373)
[error] scala.tools.nsc.typechecker.Typers$Typer.typedTemplate(Typers.scala:2030)
[error] scala.tools.nsc.typechecker.Typers$Typer.typedClassDef(Typers.scala:1843)
[error] scala.tools.nsc.typechecker.Typers$Typer.typed1(Typers.scala:5646)
[error] scala.tools.nsc.typechecker.Typers$Typer.typed(Typers.scala:5726)
[error] scala.tools.nsc.typechecker.Typers$Typer.typedStat$1(Typers.scala:5790)
[error] scala.tools.nsc.typechecker.Typers$Typer.$anonfun$typedStats$10(Typers.scala:3373)
[error] scala.tools.nsc.typechecker.Typers$Typer.typedStats(Typers.scala:3373)
[error] scala.tools.nsc.typechecker.Typers$Typer.typedPackageDef$1(Typers.scala:5356)
[error] scala.tools.nsc.typechecker.Typers$Typer.typed1(Typers.scala:5649)
[error] scala.tools.nsc.typechecker.Typers$Typer.typed(Typers.scala:5726)
[error] scala.tools.nsc.typechecker.Analyzer$typerFactory$TyperPhase.apply(Analyzer.scala:114)
[error] scala.tools.nsc.Global$GlobalPhase.applyPhase(Global.scala:448)
[error] scala.tools.nsc.typechecker.Analyzer$typerFactory$TyperPhase.run(Analyzer.scala:103)
[error] scala.tools.nsc.Global$Run.compileUnitsInternal(Global.scala:1498)
[error] scala.tools.nsc.Global$Run.compileUnits(Global.scala:1482)
[error] scala.tools.nsc.Global$Run.compileSources(Global.scala:1475)
[error] scala.tools.nsc.Global$Run.compileFiles(Global.scala:1580)
[error] xsbt.CachedCompiler0.run(CompilerBridge.scala:163)
[error] xsbt.CachedCompiler0.run(CompilerBridge.scala:134)
[error] xsbt.CompilerBridge.run(CompilerBridge.scala:39)
[error] sbt.internal.inc.AnalyzingCompiler.compile(AnalyzingCompiler.scala:92)
[error] sbt.internal.inc.MixedAnalyzingCompiler.$anonfun$compile$7(MixedAnalyzingCompiler.scala:186)
[error] scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)
[error] sbt.internal.inc.MixedAnalyzingCompiler.timed(MixedAnalyzingCompiler.scala:241)
[error] sbt.internal.inc.MixedAnalyzingCompiler.$anonfun$compile$4(MixedAnalyzingCompiler.scala:176)
[error] sbt.internal.inc.MixedAnalyzingCompiler.$anonfun$compile$4$adapted(MixedAnalyzingCompiler.scala:157)
[error] sbt.internal.inc.JarUtils$.withPreviousJar(JarUtils.scala:239)
[error] sbt.internal.inc.MixedAnalyzingCompiler.compileScala$1(MixedAnalyzingCompiler.scala:157)
[error] sbt.internal.inc.MixedAnalyzingCompiler.compile(MixedAnalyzingCompiler.scala:204)
[error] sbt.internal.inc.IncrementalCompilerImpl.$anonfun$compileInternal$1(IncrementalCompilerImpl.scala:573)
[error] sbt.internal.inc.IncrementalCompilerImpl.$anonfun$compileInternal$1$adapted(IncrementalCompilerImpl.scala:573)
[error] sbt.internal.inc.Incremental$.$anonfun$apply$5(Incremental.scala:173)
[error] sbt.internal.inc.Incremental$.$anonfun$apply$5$adapted(Incremental.scala:171)
[error] sbt.internal.inc.Incremental$$anon$2.run(Incremental.scala:458)
[error] sbt.internal.inc.IncrementalCommon$CycleState.next(IncrementalCommon.scala:116)
[error] sbt.internal.inc.IncrementalCommon$$anon$1.next(IncrementalCommon.scala:56)
[error] sbt.internal.inc.IncrementalCommon$$anon$1.next(IncrementalCommon.scala:52)
[error] sbt.internal.inc.IncrementalCommon.cycle(IncrementalCommon.scala:261)
[error] sbt.internal.inc.Incremental$.$anonfun$incrementalCompile$8(Incremental.scala:413)
[error] sbt.internal.inc.Incremental$.withClassfileManager(Incremental.scala:498)
[error] sbt.internal.inc.Incremental$.incrementalCompile(Incremental.scala:400)
[error] sbt.internal.inc.Incremental$.apply(Incremental.scala:165)
[error] sbt.internal.inc.IncrementalCompilerImpl.compileInternal(IncrementalCompilerImpl.scala:573)
[error] sbt.internal.inc.IncrementalCompilerImpl.$anonfun$compileIncrementally$1(IncrementalCompilerImpl.scala:491)
[error] sbt.internal.inc.IncrementalCompilerImpl.handleCompilationError(IncrementalCompilerImpl.scala:332)
[error] sbt.internal.inc.IncrementalCompilerImpl.compileIncrementally(IncrementalCompilerImpl.scala:420)
[error] sbt.internal.inc.IncrementalCompilerImpl.compile(IncrementalCompilerImpl.scala:137)
[error] sbt.Defaults$.compileIncrementalTaskImpl(Defaults.scala:2176)
[error] sbt.Defaults$.$anonfun$compileIncrementalTask$2(Defaults.scala:2133)
[error] sbt.internal.io.Retry$.apply(Retry.scala:40)
[error] sbt.internal.io.Retry$.apply(Retry.scala:23)
[error] sbt.internal.server.BspCompileTask$.compute(BspCompileTask.scala:31)
[error] sbt.Defaults$.$anonfun$compileIncrementalTask$1(Defaults.scala:2129)
[error] scala.Function1.$anonfun$compose$1(Function1.scala:49)
[error] sbt.internal.util.$tilde$greater.$anonfun$$u2219$1(TypeFunctions.scala:62)
[error] sbt.std.Transform$$anon$4.work(Transform.scala:68)
[error] sbt.Execute.$anonfun$submit$2(Execute.scala:282)
[error] sbt.internal.util.ErrorHandling$.wideConvert(ErrorHandling.scala:23)
[error] sbt.Execute.work(Execute.scala:291)
[error] sbt.Execute.$anonfun$submit$1(Execute.scala:282)
[error] sbt.ConcurrentRestrictions$$anon$4.$anonfun$submitValid$1(ConcurrentRestrictions.scala:265)
[error] sbt.CompletionService$$anon$2.call(CompletionService.scala:64)
[error] java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264)
[error] java.base/java.util.concurrent.Executors$RunnableAdapter.call(Executors.java:515)
[error] java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264)
[error] java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1130)
[error] java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:630)
[error] java.base/java.lang.Thread.run(Thread.java:832)
[error]
[error] java.io.IOError: java.lang.RuntimeException: /packages cannot be represented as URI
[error] at java.base/jdk.internal.jrtfs.JrtPath.toUri(JrtPath.java:176)
[error] at scala.tools.nsc.classpath.JrtClassPath.asURLs(DirectoryClassPath.scala:213)
[error] at scala.tools.nsc.classpath.AggregateClassPath.$anonfun$asURLs$1(AggregateClassPath.scala:64)
[error] at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:244)
[error] at scala.collection.Iterator.foreach(Iterator.scala:941)
[error] at scala.collection.Iterator.foreach$(Iterator.scala:941)
[error] at scala.collection.AbstractIterator.foreach(Iterator.scala:1429)
[error] at scala.collection.IterableLike.foreach(IterableLike.scala:74)
[error] at scala.collection.IterableLike.foreach$(IterableLike.scala:73)
[error] at scala.collection.AbstractIterable.foreach(Iterable.scala:56)
[error] at scala.collection.TraversableLike.flatMap(TraversableLike.scala:244)
[error] at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:241)
[error] at scala.collection.AbstractTraversable.flatMap(Traversable.scala:108)
[error] at scala.tools.nsc.classpath.AggregateClassPath.asURLs(AggregateClassPath.scala:64)
[error] Caused by: java.lang.RuntimeException: /packages cannot be represented as URI
[error] at java.base/jdk.internal.jrtfs.JrtPath.toUri(JrtPath.java:176)
[error] at scala.tools.nsc.classpath.JrtClassPath.asURLs(DirectoryClassPath.scala:213)
[error] at scala.tools.nsc.classpath.AggregateClassPath.$anonfun$asURLs$1(AggregateClassPath.scala:64)
[error] at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:244)
[error] at scala.collection.Iterator.foreach(Iterator.scala:941)
[error] at scala.collection.Iterator.foreach$(Iterator.scala:941)
[error] at scala.collection.AbstractIterator.foreach(Iterator.scala:1429)
[error] at scala.collection.IterableLike.foreach(IterableLike.scala:74)
[error] at scala.collection.IterableLike.foreach$(IterableLike.scala:73)
[error] at scala.collection.AbstractIterable.foreach(Iterable.scala:56)
[error] at scala.collection.TraversableLike.flatMap(TraversableLike.scala:244)
[error] at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:241)
[error] at scala.collection.AbstractTraversable.flatMap(Traversable.scala:108)
[error] at scala.tools.nsc.classpath.AggregateClassPath.asURLs(AggregateClassPath.scala:64)
[error] (hardfloat / Compile / compileIncremental) java.io.IOError: java.lang.RuntimeException: /packages cannot be represented as URI
[error] Total time: 4 s, completed Sep 10, 2021, 11:19:32 AM
make: *** [Makefile:174: workspace/rocket64b2/system-nexys-video/Vivado.Rocket64b2.fir] Error 1

I'm not sure which version of jdk i should use. jdk14 seems to be incompatible with sbt and jdk 11 (or even 8) fails also due to file versions.

Can anybody help?

Add a custom rocc, linux boot fail

Hi, I add my custom rocc to the rocket tile, and the bitstream was generated successfully. But the Linux boot step encounters some problems, as shown below.

So, do I need to modify some config and rebuild the Linux SD card?
If need, could you give me some advice?

Compile error for Nexys Video rocket64b8

Logs:

INFO: [Vivado_Tcl 4-198] DRC finished with 3 Errors, 8 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
INFO: [Common 17-83] Releasing license: Implementation
77 Infos, 17 Warnings, 7 Critical Warnings and 4 Errors encountered.
place_design failed
place_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 5897.266 ; gain = 0.000 ; free physical = 48196 ; free virtual = 57096
ERROR: [Common 17-39] 'place_design' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Sat Aug  8 01:50:11 2020...
[Sat Aug  8 01:57:14 2020] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'
Command: write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit {up 0x0 workspace/rocket64b8/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit} -file workspace/rocket64b8/nexys-video-riscv.mcs -force
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile workspace/rocket64b8/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit
ERROR: [Bitstream 40-47] File workspace/rocket64b8/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit does not exist.
ERROR: [Bitstream 40-46] File workspace/rocket64b8/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit cannot be opened for input.
ERROR: [Writecfgmem 68-7] Could not load bitfile workspace/rocket64b8/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit.
3 Infos, 2 Warnings, 0 Critical Warnings and 3 Errors encountered.
write_cfgmem failed
ERROR: [Common 17-39] 'write_cfgmem' failed due to earlier errors.

    while executing
"write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit "up 0x0 workspace/rocket64b8/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv..."
    (file "workspace/rocket64b8/vivado-nexys-video-riscv/make-bitstream.tcl" line 5)
Makefile:253: recipe for target 'workspace/rocket64b8/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit' failed
make: *** [workspace/rocket64b8/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit] Error 1

Thanks!

I used a 8G sd card,when run " ./mk-sd-card",it shows"gzip: stdin: not in gzip format tar: Child returned status 1 tar: Error is not recoverable: exiting now"

Kingston 8GB micro SDC 10G 2/8GB; then I choosed sony 128GB SF-G1UX2/T3 CN,it shows the same error.

Can not install pip

Hi,when I tried to install pip and I encountered this error:

I tried both "sudo apt-get install" and "apt-get --fix-missing".But It still shows that error.

I want to set up the tvm environment on the board, so I need to install pip first and then install NumPy, etc. So have you ever encounter this error? Or do you have any suggestions to install some python packages in the embedded Linux without pip?

Thanks for your time! Any kind reply is appreciated~

32bits OS support

Hi, besides changing the riscv toolchain, what else needs to be changed to run the 32-bit riscv OS

GPIO support

Could you please add GPIO support? Or, give us a development pipeline. Thanks a lot.

compile error

under the vivado2019.2 env, i run the follow command: make CONFIG=rocket64b2 BOARD=nexys-video bitstream
,then it occured errors...,

echo "open_project workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.xpr" >workspace/rocket64b2/vivado-nexys-video-riscv/make-bitstream.tcl
echo "update_compile_order -fileset sources_1" >>workspace/rocket64b2/vivado-nexys-video-riscv/make-bitstream.tcl
echo "set_param general.maxThreads 4" >>workspace/rocket64b2/vivado-nexys-video-riscv/make-bitstream.tcl
echo "launch_runs impl_1 -to_step write_bitstream -jobs 4" >>workspace/rocket64b2/vivado-nexys-video-riscv/make-bitstream.tcl
echo "wait_on_run impl_1" >>workspace/rocket64b2/vivado-nexys-video-riscv/make-bitstream.tcl
echo "write_cfgmem -format mcs -interface SPIx4 -size 32 -loadbit "up 0x0 workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit" -file workspace/rocket64b2/nexys-video-riscv.mcs -force" >>workspace/rocket64b2/vivado-nexys-video-riscv/make-bitstream.tcl
env XILINX_LOCAL_USER_DATA=no vivado -mode batch -nojournal -nolog -notrace -quiet -source workspace/rocket64b2/vivado-nexys-video-riscv/make-bitstream.tcl
INFO: [Common 17-1239] XILINX_LOCAL_USER_DATA is set to 'no'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'riscv_io_axi_m_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_io_axi_m_0/riscv_io_axi_m_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_io_axi_m_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_io_axi_m_0/riscv_io_axi_m_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_io_axi_m_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_io_axi_m_0/riscv_io_axi_m_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_io_axi_m_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_io_axi_m_0/riscv_io_axi_m_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_io_axi_m_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_io_axi_m_0/riscv_io_axi_m_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_UART_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_UART_0/riscv_UART_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_UART_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_UART_0/riscv_UART_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_UART_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_UART_0/riscv_UART_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_UART_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_UART_0/riscv_UART_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_UART_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_UART_0/riscv_UART_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_RocketChip_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_RocketChip_0/riscv_RocketChip_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_RocketChip_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_RocketChip_0/riscv_RocketChip_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_RocketChip_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_RocketChip_0/riscv_RocketChip_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_RocketChip_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_RocketChip_0/riscv_RocketChip_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_RocketChip_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_RocketChip_0/riscv_RocketChip_0_sim_netlist.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_clk_wiz_0_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_clk_wiz_0_0/riscv_clk_wiz_0_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_clk_wiz_0_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_clk_wiz_0_0/riscv_clk_wiz_0_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_clk_wiz_0_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_clk_wiz_0_0/riscv_clk_wiz_0_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_clk_wiz_0_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_clk_wiz_0_0/riscv_clk_wiz_0_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_clk_wiz_0_0' generated file not found '/home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.srcs/sources_1/bd/riscv/ip/riscv_clk_wiz_0_0/riscv_clk_wiz_0_0_sim_netlist.vhdl'. Please regenerate to continue.
open_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:52 . Memory (MB): peak = 1601.152 ; gain = 105.641 ; free physical = 1697 ; free virtual = 4091
update_compile_order: Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1697.199 ; gain = 96.047 ; free physical = 1694 ; free virtual = 4088
INFO: [IP_Flow 19-5642] Done with IP cache export for multiple IPs
[Tue Mar 23 00:13:38 2021] Launched riscv_io_axi_m_0_synth_1, riscv_UART_0_synth_1, riscv_RocketChip_0_synth_1, riscv_clk_wiz_0_0_synth_1, synth_1...
Run output will be captured here:
riscv_io_axi_m_0_synth_1: /home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/riscv_io_axi_m_0_synth_1/runme.log
riscv_UART_0_synth_1: /home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/riscv_UART_0_synth_1/runme.log
riscv_RocketChip_0_synth_1: /home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/riscv_RocketChip_0_synth_1/runme.log
riscv_clk_wiz_0_0_synth_1: /home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/riscv_clk_wiz_0_0_synth_1/runme.log
synth_1: /home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/synth_1/runme.log
[Tue Mar 23 00:13:39 2021] Launched impl_1...
Run output will be captured here: /home/risc/workspace/vivado-risc-v/workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:32 ; elapsed = 00:00:30 . Memory (MB): peak = 1712.203 ; gain = 15.004 ; free physical = 1674 ; free virtual = 4068
[Tue Mar 23 00:13:39 2021] Waiting for impl_1 to finish...
[Tue Mar 23 00:27:38 2021] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'riscv_RocketChip_0_synth_1'
wait_on_run: Time (s): cpu = 00:00:00.07 ; elapsed = 00:14:21 . Memory (MB): peak = 1712.203 ; gain = 0.000 ; free physical = 830 ; free virtual = 1232
Command: write_cfgmem -format mcs -interface SPIx4 -size 32 -loadbit {up 0x0 workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit} -file workspace/rocket64b2/nexys-video-riscv.mcs -force
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit
ERROR: [Bitstream 40-47] File workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit does not exist.
ERROR: [Bitstream 40-46] File workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit cannot be opened for input.
ERROR: [Writecfgmem 68-7] Could not load bitfile workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit.
5 Infos, 21 Warnings, 0 Critical Warnings and 3 Errors encountered.
write_cfgmem failed
write_cfgmem: Time (s): cpu = 00:00:00 ; elapsed = 00:00:45 . Memory (MB): peak = 1712.203 ; gain = 0.000 ; free physical = 645 ; free virtual = 1172
ERROR: [Common 17-39] 'write_cfgmem' failed due to earlier errors.

while executing

"write_cfgmem -format mcs -interface SPIx4 -size 32 -loadbit "up 0x0 workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_..."
(file "workspace/rocket64b2/vivado-nexys-video-riscv/make-bitstream.tcl" line 6)
make: *** [Makefile:300: workspace/rocket64b2/vivado-nexys-video-riscv/nexys-video-riscv.runs/impl_1/riscv_wrapper.bit] Error 1

Other FPGAs

Is it possible to use these implementations of ZCU102?
if yes, then what are the changes required to make it run.

Thanks in advance!

After programing the FPGA flash memory,it seems no message output with the serial port emulator.

Information: Nexys A7 100t,the done led is on, the serial port cable is connected and the port is configured to 115200, 8 bit, no parity, 1 bit stop, no flow control.
I don't know why,could you give me some suggestions? Thanks.

Makefile stops executing after generating HDL

When I run make CONFIG=rocket64x1 BOARD=nexys-video bitstream

Execution stops after the generate Rocket SoC HDL section.

I get the following output in my console after Makefile: 200 :

Computed transform order in: 3171.4 ms

The next make target, generate Rocket SoC Wrapper is not executed.

I am running in Ubuntu 20 LTS and Vivado 2019.1

Please suggest a solution

Increase FIFO size in UART

Can we increase the FIFO size by configuring "fifo_ptr_bits" parameter in uart.v without any complications in working on the UART controller?

When we using Vitis 2021.1, wouldn't we need that riscv-2021.1.tcl files?

Hello, I am paran lee.

I am enthusiast risc-v and hardware IP. and i have a vc707 board as a hobby.

Follow as guide, then he needed riscv-2021.1.tcl.

couldn't read file "../../board/vc707/riscv-2021.1.tcl": no such file or directory

Shall I fix it once I get back and request a pull request?

@eugene-tarassov Thank you so much for writing such a great guide! :)

kim@kim-GL702ZC:~/vivado-risc-v$ make CONFIG=rocket64z2m BOARD=vc707 bitstream
make -C rocket-chip/firrtl SBT="java -Xmx4G -Xss8M  -jar /home/kim/vivado-risc-v/rocket-chip/sbt-launch.jar" build-scala
make[1]: 디렉터리 '/home/kim/vivado-risc-v/rocket-chip/firrtl' 들어감
java -Xmx4G -Xss8M  -jar /home/kim/vivado-risc-v/rocket-chip/sbt-launch.jar "assembly"
[info] Loading global plugins from /home/kim/.sbt/1.0/plugins
[info] Loading settings for project firrtl-build from plugins.sbt ...
[info] Loading project definition from /home/kim/vivado-risc-v/rocket-chip/firrtl/project

# ... 

[success] Total time: 147 s (02:27), completed 2021. 8. 1. 오전 12:45:25
rm workspace/bootrom.img
java -Xmx12G -Xss8M  -cp rocket-chip/firrtl/utils/bin/firrtl.jar:target/scala-2.12/classes:rocket-chip/rocketchip.jar firrtl.stage.FirrtlMain -i workspace/rocket64z2m/system-vc707/Vivado.Rocket64z2m.fir -o system-vc707.v -X verilog --infer-rw RocketSystem --repl-seq-mem \
  -c:RocketSystem:-o:workspace/rocket64z2m/system.conf \
  -faf workspace/rocket64z2m/system.anno.json \
  -td workspace/rocket64z2m/ \
  -fct firrtl.passes.InlineInstances
rocket-chip/scripts/vlsi_mem_gen workspace/rocket64z2m/system.conf >workspace/rocket64z2m/srams.v
mkdir -p vhdl-wrapper/bin
javac -g -nowarn \
  -sourcepath vhdl-wrapper/src -d vhdl-wrapper/bin \
  -classpath vhdl-wrapper/antlr-4.8-complete.jar \
  vhdl-wrapper/src/net/largest/riscv/vhdl/Main.java
java -Xmx4G -Xss8M  -cp \
  vhdl-wrapper/src:vhdl-wrapper/bin:vhdl-wrapper/antlr-4.8-complete.jar \
  net.largest.riscv.vhdl.Main -m Rocket64z2m \
  workspace/rocket64z2m/system-vc707.v >workspace/rocket64z2m/rocket.vhdl
echo "set vivado_board_name vc707" >workspace/rocket64z2m/system-vc707.tcl
echo "set vivado_board_part xilinx.com:vc707:part0:1.4" >>workspace/rocket64z2m/system-vc707.tcl
echo "set xilinx_part xc7vx485tffg1761-2" >>workspace/rocket64z2m/system-vc707.tcl
echo "set rocket_module_name Rocket64z2m" >>workspace/rocket64z2m/system-vc707.tcl
echo "set riscv_clock_frequency 40.0" >>workspace/rocket64z2m/system-vc707.tcl
echo 'cd [file dirname [file normalize [info script]]]' >>workspace/rocket64z2m/system-vc707.tcl
echo 'source ../../vivado.tcl' >>workspace/rocket64z2m/system-vc707.tcl
if [ ! -e workspace/rocket64z2m/vivado-vc707-riscv ] ; then env XILINX_LOCAL_USER_DATA=no vivado -mode batch -nojournal -nolog -notrace -quiet -source workspace/rocket64z2m/system-vc707.tcl ; fi
INFO: [Common 17-1239] XILINX_LOCAL_USER_DATA is set to 'no'.
couldn't read file "../../board/vc707/riscv-2021.1.tcl": no such file or directory
    while executing
"source ../../board/${vivado_board_name}/riscv-${current_vivado_version}.tcl"
    (file "../../vivado.tcl" line 79)
make: *** [Makefile:239: workspace/rocket64z2m/vivado-vc707-riscv/timestamp.txt] error 1

Makefile:262: recipe for target 'workspace/rocket32s1/vivado-genesys2-riscv/genesys2-riscv.runs/impl_1/riscv_wrapper.bit' failed

when i run make CONFIG=rocket32s1 BOARD=genesys2 bitstream

INFO: [Common 17-344] 'launch_runs' was cancelled
INFO: [Common 17-344] 'source' was cancelled
Makefile:262: recipe for target 'workspace/rocket32s1/vivado-genesys2-riscv/genesys2-riscv.runs/impl_1/riscv_wrapper.bit' failed
make: *** [workspace/rocket32s1/vivado-genesys2-riscv/genesys2-riscv.runs/impl_1/riscv_wrapper.bit] Error 1

my env: ubuntu 18.04.5 LTS,vivado 2020.1
i run step by step,how should i fix this problem,thank you for your help!

u-boot compile error

when i use my riscv-linux- toolchain to compile u-boot, there is one error, "arch/riscv/cpu/mtrap.S:67: error: Instruction csrr requires absolute expression". Could you give me some advice, thank you.

Nexys Video cannot boot Linux

Hello, when I boot with SD card, the board cannot boot Linux, and it displays some errors like this
the first part

[   10.166214] 9pnet: Installing 9P2000 support
[   10.171324] Key type dns_resolver registered
[   10.218466] Freeing unused kernel memory: 232K
[   10.222030] mmc0: host does not support reading read-only switch, assuming write-enable
[   10.230936] Run /init as init process
[   10.234486] mmc0: new high speed SDHC card at address 5048
[   10.249550] mmcblk0: mmc0:5048 SD16G 14.4 GiB 
[   10.380304] blk_update_request: I/O error, dev mmcblk0, sector 0 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   10.411564] blk_update_request: I/O error, dev mmcblk0, sector 1 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   10.443152] blk_update_request: I/O error, dev mmcblk0, sector 2 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   10.474474] blk_update_request: I/O error, dev mmcblk0, sector 3 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   10.505794] blk_update_request: I/O error, dev mmcblk0, sector 4 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   10.537038] blk_update_request: I/O error, dev mmcblk0, sector 5 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   10.568482] blk_update_request: I/O error, dev mmcblk0, sector 6 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
Loading, please wait...

the second part

Begin: Running /scripts/local-block ... done.
[   71.205838] Buffer I/O error on dev mmcblk0, logical block 3780592, async page read
[   71.620102] Buffer I/O error on dev mmcblk0, logical block 3780592, async page read
Begin: Running /scripts/local-block ... done.
[   73.258002] Buffer I/O error on dev mmcblk0, logical block 3780592, async page read
[   73.672090] Buffer I/O error on dev mmcblk0, logical block 3780592, async page read
Begin: Running /scripts/local-block ... done.
[   74.979542] print_req_error: 86 callbacks suppressed
[   74.984392] blk_update_request: I/O error, dev mmcblk0, sector 30244736 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
[   75.017256] blk_update_request: I/O error, dev mmcblk0, sector 30244737 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
[   75.050016] blk_update_request: I/O error, dev mmcblk0, sector 30244738 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
[   75.082648] blk_update_request: I/O error, dev mmcblk0, sector 30244739 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
[   75.115292] blk_update_request: I/O error, dev mmcblk0, sector 30244740 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
[   75.148144] blk_update_request: I/O error, dev mmcblk0, sector 30244741 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
[   75.181166] blk_update_request: I/O error, dev mmcblk0, sector 30244742 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
[   75.213994] blk_update_request: I/O error, dev mmcblk0, sector 30244743 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
[   75.252128] blk_update_request: I/O error, dev mmcblk0, sector 30244736 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   75.284382] blk_update_request: I/O error, dev mmcblk0, sector 30244737 op 0x0:(READ) flags 0x0 phys_seg 1 prio class 0
[   75.425930] Buffer I/O error on dev mmcblk0, logical block 3780592, async page read
[   75.840078] Buffer I/O error on dev mmcblk0, logical block 3780592, async page read
Begin: Running /scripts/local-block ... done.
[   77.476068] Buffer I/O error on dev mmcblk0, logical block 3780592, async page read
[   77.889882] Buffer I/O error on dev mmcblk0, logical block 3780592, async page read
done.
[   78.432032] Buffer I/O error on dev mmcblk0, logical block 3780592, async page read
[   78.845992] Buffer I/O error on dev mmcblk0, logical block 3780592, async page read
Gave up waiting for root file system device.  Common problems:
 - Boot args (cat /proc/cmdline)
   - Check rootdelay= (did the system wait long enough?)
 - Missing modules (cat /proc/modules; ls /dev)
ALERT!  UUID=68d82fa1-1bb5-435f-a5e3-862176586eec does not exist.  Dropping to a shell!
(initramfs)

what should I do?

Running "make CONFIG=rocket64b2 BOARD=nexys-a7-100t bitstream" failed. As follows:

[error] lmcoursier.internal.shaded.coursier.error.FetchError$DownloadingArtifacts: Error fetching artifacts:
[error] https://repo.scala-sbt.org/scalasbt/sbt-plugin-releases/com.eed3si9n/sbt-sriracha/scala_2.12/sbt_1.0/0.1.0/docs/sbt-sriracha-javadoc.jar: download error: Caught javax.net.ssl.SSLHandshakeException: Remote host terminated the handshake (Remote host terminated the handshake) while downloading https://repo.scala-sbt.org/scalasbt/sbt-plugin-releases/com.eed3si9n/sbt-sriracha/scala_2.12/sbt_1.0/0.1.0/docs/sbt-sriracha-javadoc.jar
......
Killed
make: *** [Makefile:211: workspace/rocket64b2/system.dts] Error 137

Gemmini running issue ?

Hello. I am working on running the Gemmini accelerator using the uploaded material.
(Gemminis SW in their github and my device is vc707 rev1.1)
The DNN code in Gemmini git is compiled and executed.
But when the part corresponding to the accelerator is executed, the device stops.
(Gemmni's linux softwares such as matmul)

Do you have any experience with this?

Peripheral device cannot work

Hello,

1. I have added axi-ps2 IP into the block design, which can be found in (https://github.com/Digilent/Nexys-Video-AXI-PS2-Keyboard), but there is no Linux driver for this IP.
2. I read the documents in the IP directory, and changed the 'Register offsets for the xps2 device' of the xilinx_ps2.c which can be found in vivado-risc-v/linux-stable/drivers/input/serio/xilinx_ps2.c.
3. After doing this, I can't use the keyboard in the FPGA, I don't know whether the step I do is right or not?

Linux cannot boot after a custom RoCC added

Hi, I add a custom RoCC to the rocket tile, and the bitstream is generated successfully. But when I want to boot the Linux, the serial port shows nothing, even the opensbi logo is gone.
So could you give me some advice on how to debug and what kind of signals I need to pay attention to? Because I just can not find where to shart.
And I find there are thousands of timing constraints no met. But fix them one by one seems impossible. So what is your opinion on this timing problem?
Thanks a lot.

java.lang.ClassNotFoundException: freechips.rocketchip.system.Generator

Hello, Thank you for doing this meaning for work to make run RISCV-SoC on the FPGA board so conveniently.
And I encountered a problem when runned the "make CONFIG=rocket64b1 BOARD=vc707 bitstream" command.The output log is listed as fellows:
make: Warning: File 'rocket-chip/src/main/scala/tile/LCM.scala' has modification time 15013 s in the future
cd rocket-chip && ( git apply -R --check ../patches/rocket-chip.patch 2>/dev/null || git apply ../patches/rocket-chip.patch )
cd generators/gemmini && ( git apply -R --check ../../patches/gemmini.patch 2>/dev/null || git apply ../../patches/gemmini.patch )
mkdir -p workspace/rocket64b1/tmp
cp rocket-chip/bootrom/bootrom.img workspace/bootrom.img
java -Xmx8G -Xss8M -jar /home/xiongwu/Desktop/fpga/vivado-risc-v/rocket-chip/sbt-launch.jar "runMain freechips.rocketchip.system.Generator -td workspace/rocket64b1/tmp -T Vivado.RocketSystem -C Vivado.Rocket64b1"
Warning: could not parse http_proxy setting: java.net.MalformedURLException: unknown protocol: socks5
Warning: could not parse https_proxy setting: java.net.MalformedURLException: unknown protocol: socks5
[info] welcome to sbt 1.4.4 (Ubuntu Java 11.0.11)
[info] loading settings for project vivado-risc-v-build from plugins.sbt ...
[info] loading project definition from /home/xiongwu/Desktop/fpga/vivado-risc-v/project
[info] loading settings for project vivado from build.sbt ...
[info] loading settings for project rocketchip from build.sbt ...
[info] loading settings for project testchipip from build.sbt ...
[info] loading settings for project boom from build.sbt ...
[info] loading settings for project gemmini from build.sbt ...
[info] loading settings for project api-config-chipsalliance from build.sbt ...
[info] loading settings for project hardfloat from build.sbt ...
[info] resolving key references (11260 settings) ...
Using addons:
[info] set current project to vivado (in build file:/home/xiongwu/Desktop/fpga/vivado-risc-v/)
[warn] there are 5 keys that are not used by any other settings/tasks:
[warn]
[warn] * api-config-chipsalliance / traceLevel
[warn] +- /home/xiongwu/Desktop/fpga/vivado-risc-v/rocket-chip/build.sbt:16
[warn] * docs / traceLevel
[warn] +- /home/xiongwu/Desktop/fpga/vivado-risc-v/rocket-chip/build.sbt:16
[warn] * hardfloat / traceLevel
[warn] +- /home/xiongwu/Desktop/fpga/vivado-risc-v/rocket-chip/build.sbt:16
[warn] * rocket-macros / traceLevel
[warn] +- /home/xiongwu/Desktop/fpga/vivado-risc-v/rocket-chip/build.sbt:16
[warn] * rocketchip / traceLevel
[warn] +- /home/xiongwu/Desktop/fpga/vivado-risc-v/rocket-chip/build.sbt:16
[warn]
[warn] note: a setting might still be used by a command; to exclude a key from this lintUnused check
[warn] either append it to Global / excludeLintKeys or call .withRank(KeyRanks.Invisible) on the key
[info] running freechips.rocketchip.system.Generator -td workspace/rocket64b1/tmp -T Vivado.RocketSystem -C Vivado.Rocket64b1
[error] (run-main-0) java.lang.ClassNotFoundException: freechips.rocketchip.system.Generator
[error] java.lang.ClassNotFoundException: freechips.rocketchip.system.Generator
[error] at java.base/java.net.URLClassLoader.findClass(URLClassLoader.java:471)
[error] stack trace is suppressed; run last Compile / bgRunMain for the full output
[error] Nonzero exit code: 1
[error] (Compile / runMain) Nonzero exit code: 1
[error] Total time: 3 s, completed Aug 12, 2021, 4:41:27 PM
make: *** [Makefile:154: workspace/rocket64b1/system.dts] Error 1

And I checked that there is a Generator object in the rokect-chip source code,it is located at rocket-chip/src/main/scala/system/RocketChipStageGenerator.scala

So do you have any suggestions for solving this confusing problem?

AC701 Support

Hi,

My research lab is still using some old AC701 boards, so I adapted some of your existing configurations (such as the nexys-a7-100t) to support it.

I edited riscv-2020.2.tcl to setup the ddr3 MIG for the AC701. I imported the MIG configuration from files referenced in this tutorial. However, I don't know how to implement ethernet, so I removed it from the block diagram and device tree.

I have edited the constraints files top.xdc, uart.xdc, and sdc.xdc based on the ac701 manual.

My system boots your compiled linux images just fine; thanks for this great repo!

I was wondering if I could make a pull request (once I clean up some of my changes). Having more examples of supported boards might help people implement new ones.

Or, since I might not be able to test AC701 functionality every time your repository changes, I can keep my modifications as a fork.

run baremetal or linux software

hello,

I have already deployed the rocket64b2gem on vc707 and can boot Linux. Then I want to test the Gemmini on vc707. I have built the Gemmini test binaries both for baremetal and linux according to the gemmini @ d4a2990. How can I run those test binaries on vc707?
much appreciated.

Top module not set for fileset 'source_1'

Under the vivado 2018.2 env, it occurred error when i run
make CONFIG=rocket64b2 BOARD=nexys-video bitstream

Scanning sources...
Finished scanning sources
CRITICAL WARNING: [filemgmt 20-730] Could not find a top module in the fileset sources_1.
Resolution: With the gui up, review the source files in the Sources window. Use Add Sources to add any needed sources. If the files are disabled, enable them. You can also select the file and choose Set Used In from the pop-up menu. Review if they are being used at the proper points of the flow.
CRITICAL WARNING: [filemgmt 20-730] Could not find a top module in the fileset sources_1.
Resolution: With the gui up, review the source files in the Sources window. Use Add Sources to add any needed sources. If the files are disabled, enable them. You can also select the file and choose Set Used In from the pop-up menu. Review if they are being used at the proper points of the flow.
ERROR: [Common 17-70] Application Exception: Top module not set for fileset 'sources_1'. Please ensure that a valid value is provided for 'top'. The value for 'top' can be set/changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command (e.g. set_property top [current_fileset]).

---

I think 'source_1' means the fileset 'rocket64', and all the file is in next picture

What's the top module name and how I fix it?

The frequency of rocketx1 with genesys2

Hello, how can I find out the frequency of the cpu written to the fpga after the vivado synthesis? I used the config "rocket64x1" and genesys2 board. Thank you.

Vivado patch releases

Thank you for making this splendid archive available.

If you use a Vivado patch release (e.g. 2020.1.1), then the board specific file (e.g. board/vc707/riscv-2020.1.1.tcl) is not found and the make fails. I was able to make progress by copying riscv-2020.1.1.tcl from risk-2020.1.tcl but I wonder if there is a more elegant way to do it automatically ?

How to connect Internet on VC707 board

I use the released vc707 bit and the ./mk-sd-cad command, the Linux can boot successfully.
And I use the internet cable to connect the board and the wired network port.
But when I try to connect to the Internet, as I use the command "sudo ping 182.61.200.6", it returns "the network is unreachable".

And the IP address is as below:

And I noticed that :

It seems that I need to change some MAC addresses and rebuild the bitstream. But what exactly should I do to connect the board to the Internet?

Thanks a lot!