fabriziotappero/free-range-vhdl-book

Latex source files of the open-source book FREE RANGE VHDL

Hi there, my name is Fabrizio, I am an electrical engineer with a PhD from USNW and this is a little bit about myself.

• 🔨 I’m currently working on C++ tools for data manipulation in the ADAS sector
• 👀 On the side I’m learning about the Golang and WebAssembly.
• 💖 I’m looking to collaborate on electronics 🔌 and programming 📻
• 💬 Ask me about programming of embedded systems and similar
• 📫 How to reach me: [email protected]
• ⚡ Fun fact: I sometimes make 🎥 short films

Languages/Tools I'm Familiar With

Published Works

My Best Public Effort

A VHDL Programming Book (240 ⭐) and a Searchable VHDL Core Database (315 ⭐) with 800+ VHDL/Verilog open-source IP projects.

free-range-vhdl-book's Issues

space between overlines

There seem to be several places where an overline (inversion) one one literal merges with an overline on another.
e.g. 5.4.3 Example 12. This should read A \overline{B} \overline{C} but appears as A \overline{BC} which is different equation.

Not sure the right way to fix it - \overline{B}~\overline{C} works but isn't great kerning-wise - that's why I didn't submit a pull request.

clean.cmd has `del *~*` which is dangerous

Free-Range-VHDL-book/clean.cmd

Line 13 in 0dff43b

del *~*

I wanted to build the book with solutions.tex, so using Windows I installed MinTex and ran the build (clean.cmd followed by compile.cmd).

I noticed that not only were the solutions absent, but several later chapters were missing.

On investigation I saw that the clean has del *~*... so does the Bash one (rm *~*), but in Windows the *~* bit is very dangerous because of short filenames: any file that has more than the standard DOS 8.3 characters gets a short name associated with it, containing a tilde. This is normally invisible, but it's a gotcha when wildcarding with tildes.

To see this in action, let's look at the output of dir /x *~* on a fresh clone:

01/13/2021  02:03                75 GITIGN~1     .gitignore
01/13/2021  02:03               717 ACKNOW~1.TEX acknowledgments.tex
01/13/2021  02:03            15,605 CHAPTE~1.TEX chapter10.tex
01/13/2021  02:03            26,527 CHAPTE~2.TEX chapter11.tex
01/13/2021  02:03            10,739 CHAPTE~3.TEX chapter12.tex
01/13/2021  02:03            10,289 CHAPTE~4.TEX chapter13.tex
01/13/2021  02:03             9,227 CHB685~1.TEX chapter14.tex
01/13/2021  02:03             1,442 CONTRI~1     contribute
01/13/2021  02:03             4,209 INTROD~1.TEX introduction.tex
01/13/2021  02:03            63,378 SOLUTI~1.TEX solutions.tex

del *~* will delete every single one of those files. If you're unlucky enough to have the .git not hidden (say after a copy) it'll try to delete that too (as it's short name is GIT~1). The subsequent build will be missing key elements.

I'm not sure what this is supposed to be matching (perhaps ~filename.ext temp files?) but *~* should NOT be present in clean.cmd

Without that del *~* line things work very normally, and I can generate the book with all the chapters and the solutions.

"ref_cards" folder is missing

I tried to typeset the master code downloaded as a zip file and got that error.
I had downloaded the zip file from the old site and copied the missing folder from the older zip file to the new pics directory and everything compiled correctly.

ps: Thanks again for the book :)

Examples and Exercise Source Code

Hello,

I thought it might be helpful if there was a repository of the source code for the examples and exercise solutions. I don't know if this would be best fit as a folder in this repository, or as a separate repository, but I am willing to help contribute to that in whatever might be the best format.

Sincerely,
Sasschary

Chapter 10 example 25 circuit figure possibly wrong

In Chapter 10, examples 24 and 25 have the same circuit. The images r_rtl/ex24.png and r_rtl/ex25.png are the same but the solution given to example 25 indicates that the circuit should have different in/out ports.

Possible mistake in solution for exercise 4.8.1d

Exercise 4.8.1d asks us to implement the product of sums for 3 and 2.
The AND2 term in the solution is as follows:
AND2 <= A OR B OR C OR NOT D;
Sorry if I'm wrong (I'm still a beginner :P), but isn't this actually a NOT 1? I think it should be AND2 <= A or B or NOT C or D

Text should include definition for \prod and \sum functions

Chapter 4 includes examples and exercises using the \prod(i,j,...) and \sum(i,j,..) notations for boolean functions, apparently meaning "and of ith, jth, ... maxterms" and "or of the ith, jth, ... minterms" respectively, but does not provide definitions for them. I was able to guess the definition of \sum by carefully examining Example 8, but had to find another textbook to understand \prod. Including at least a footnote definition would be helpful.

Note: basing this on print release 1.10 (4 May 2012), and a reading of chapter4.tex.

Doubt on listing 9.6

Hello Fabrizio,

First thing first, thank you very much for your work! I love this book!

I'm at the Generic Map chapter and I can't unwrap my head about this listing. The entity describes a generic parity checker, so I'd expect to get a 0 if I set n = 3 and x =0b111, but the architecture gives me 1:

temp := 0;
-- Unwrapped
temp := temp XOR 1; -- 0 ^ 1 = 1
temp := temp XOR 1; -- 1 ^ 1 = 0
temp := temp XOR 1; -- 0 ^ 1 = 1

Am I missing something?

Thank you!

case? statement in listing 5.12

Free-Range-VHDL-book/chapter5.tex

Lines 425 to 431 in 0dff43b

	begin
	case (ABC) is
	when "100" => F_OUT <= '1';
	when "-11" => F_OUT <= '1';
	when others => F_OUT <= '0';
	end case;
	end process my_proc;

That didn't work for me when using GHDL, it outputs 0 for 011 and 111, not 1. I found this StackOverflow question mentioning that a case? statement should be used with don't cares, however that requires VHDL-2008.

hyperlinks in the appendix are not reachable

hi there,

I just discovered that the following hyperlinks in the appendix cannot be reached.
\noindent \begin{verbatim} http://www.vhdl.org/rassp/vhdl/guidelines/vhdlqrc.pdf http://www.vhdl.org/rassp/vhdl/guidelines/1164qrc.pdf \end{verbatim}

Possible alternatives: http://www.ece.ualberta.ca/~elliott/cmpe480/refcards/1164qrc.pdf, https://www.isy.liu.se/edu/kurs/TSEA83/kursmaterial/vhdl/vhdlqrc.pdf

greets

Broken links

The links at appendix.tex:L120 and appendix.tex:L121 are broken.

Inconsistent diagram/solution for exercise 3b Chapter 9

Exercise 3b, chapter 9 diagram shows a 3to8 decoder and a 4 inputs OR gate. The solution is implemented using a 4 inputs AND gate.

Exercise solutions

Where are we to find the solutions to the exercises given in the book. I have looked through the chapters but haven't noticed any.
If there isn't any solutions yet perhaps I can contribute to a new pr with the answers appended at the end?

Thanks!

Thanks to Everyone that were part of publishing "Free Range VHDL".

Best Regards,
John W.