farukyld/sort-circuit

an RTL circuit that sorts the integer values in a momory unit connected with (almost) AXI-Lite

sort-circuit's Issues

Draw the State Diagram of the HLSM

draw the State diagram of the High Level State Machine based on the c code. following the convention specified by Digital Design Frank Vahid 2nd Edition Chp. 5.
depends on #1 #4

Update the Datapath and Controller Declaration. According to HLSM

refine the verilog codes according to HLSM diagram. there may be new inputs and outputs. or some of them can be removed.

Draw the State Diagram of the FSM

depends on #2 #4

change arithmetic units with their synthesizable equivslents

Add Internal Control Signals and Register to Handle Return State to the Controller

I designed the HLSM such that some repeated sequence of states (the ones executed when making a read request and accepting its read response, and making a write request and accepting its response following AXI-lite protocol) are functionalized like a reusable block. In order to handle that, I used a register called arg_return_state in the diagram, when I made a transition to a callable state sequence, I assigned that register the state number (the encode) of the state to return when the execution of the callable state sequence completes. and when the callable completes its execution, at the last state of its, it assigns the value inside the register arg_return_state to the register state (the state register of the controller).

and I should add the internal control signals ld_arg_return_state, sl_to_arg_return_state, sl_to_state and the register arg_return_state to the body of the controller module. the added wires' and register's name may be changed.

I have designed the overall structure of the controller module before the HLSM, now, I should refine it.

relates to #12

Implement the Controller and the Datapath

depends on #4 #3 #2

Implement the Controller

Connect the Circuit into a Test Environment and Test

depends on #5 #6

Specify the Inputs-Outputs-Registers of the Datapath and the Controller

depends on #7 #1

Implement Datapath

Implement an AXI-Lite Write Submodule

The "Implement an AXI-Lite Write Submodule" task requires creating a hardware submodule that can be seamlessly integrated into larger designs. This submodule will perform write operations over the AXI-Lite interface and will communicate with the main module (caller) through control signals.

When the main module intends to execute a write operation, it will send data, address, and a start signal to the write submodule. The submodule, in its idle state, will wait for the start signal to be asserted before initiating the write operation.

As the submodule performs the write, it ensures that data is transmitted properly and, on completion, it sends a done signal back to the main module. This done signal indicates to the main module that the submodule has finished its task.

Additionally, the submodule will provide a response signal, b_resp, to the main module, which indicates the status of the write operation, such as whether it was successful or encountered any errors.

This approach enables modularity as the submodule can be integrated into different designs with ease, and the caller-callee relationship is well-defined through the start, done, and b_resp signals.

Write C Code

Write the c code of the sorting algorithm to be executed by the circuit to draw the state diagram based on it.

Test Verilog Codes

Determine the Communication Protocol between Register File and the Circuit

Implement a Register File That the Circuit Can Communicate with

depends on #4

Write Verilog Codes

• Modify controller.v to adjust for the new state sequences
• Modify datapath.v to accommodate the changes in the controller and properly route the signals
• Update sort_circuit.v to reflect changes in controller and datapath
• Implement write_submodule.v to handle the write transactions
• Complete memory.v to ensure correct state transitions and signal handshaking
• Write a comprehensive testbench to test all modules and their interactions

test and fix bugs in the circuits

Modifiy the Controller and Datapath modules to Use the Write Submodule

Add ld_return_read_data Control Signal between Controller and Datapath

Implement a Memory Filler

this module should fill the memory with random numbers Following AXI-Lite protocol. it may not neccessarily be fpga supported. I will use random component in the logisim-evolution to simulate it. random component generates next random number in at rising clock edge.

Add Information into README File About How to Experiment with the Verilog Codes

Create the State Table

Create the state table according to HLSM diagram. this table will show the outputs and next state based on inputs and current state.