fpga-logi/logi-projects

logi-projects's Issues

missing file: bin_to_fifo.vhd

https://github.com/fpga-logi/logi-projects/blob/master/logi-camera-bin/hw/logipi/ise/logipi_bin_cam.xise
requires:
../../../../../hard-cv/hw/rtl/image/bin_to_fifo.vhd

but there is no such file

~:"

it is also linked:
https://github.com/jpiat/hard-cv/blob/master/hw/rtl/image/image_pack.vhd

Binary Counter: Initial Value Problem

The following line should be added to code(Listing 4.9). Without an initial value, the counter cannot start counting.
signal r_reg: UNSIGNED(N-1 downto 0) := (others => '0');
Same thing should be applied to the Universal Binary Counter.

Stable, Dev and missing dependencies

Jonathan,

please accept my apologies if I have misconstrued how to build these projects.
I'm only just starting and they are quite large, at least for me....
It's a little difficult for me to give sufficient but not superfluous detail, please bear with me.

I am happy to contribute to either fpga-logi or fpga-logi-dev, but both might fry my brains.
please advise...

I am trying to synthesise logi_camera_test.xise,
though I may work through all the projects,
but camera & hardCV is my concern.

using fpga-logi-dev:
logi-hard is missing directory wishbone and contents, nb clock_gen is present vv
see: https://github.com/fpga-logi-dev/logi-hard

using fpga-logi:
directory logi-projects/logi-camera-test/hw/logipi/ise/ipcore_dir/clock_gen is missing
see: https://github.com/fpga-logi/logi-projects/tree/master/logi-camera-test/hw/logipi/ise/ipcore_dir

please advise what would be the most efficient approach.

I am keen to minimise both confusion, and the number of pull requests.

many thanks once again,

~:"

logi-edu demo doesn't work properly for board R1.1

logi_edu_demo.vhd needs to contain the following modified PMOD signals for the R1.1 board for things to work properly. I'm not sure how to create a VHDL file with some sort of constant that switches things for different boards...

    PMOD1(3) <= vga_out(9);     --hsync_vga ; VGA_HS
    PMOD1(7) <= vga_out(10);    --vsync_vga ;   VGA_VS
    PMOD1(0) <= vga_out(2);     --red_vga(2);   VGA_R2
    PMOD1(4) <= vga_out(1);     --red_vga(1);   VGA_R1
    PMOD2(4) <= vga_out(0);     --red_vga(0); VGA_R0
    PMOD1(1) <= vga_out(5);     --green_vga(2); VGA_G2
    PMOD1(5) <= vga_out(4);     --green_vga(1); VGA_G1
    PMOD2(3) <= vga_out(3);     --green_vga(0); VGA_G0
    PMOD1(2) <= vga_out(8);     --blue_vga(2); VGA_B2
    PMOD1(6) <= vga_out(7);     --blue_vga(1); VGA_B1
    PMOD2(0) <= vga_out(6);     --blue_vga(0); VGA_B0

    PMOD2(5) <= sseg_edu_cathode_out(0); -- cathode 0 SEG_CRTL_A1
    PMOD2(1) <= sseg_edu_cathode_out(1); -- cathode 1 SEG_CTRL_A2
    PMOD3(0) <= sseg_edu_cathode_out(2); -- cathode 2 SEG_CTRL_A3
    PMOD3(1) <= sseg_edu_cathode_out(3); -- cathode 3 SEG_CTRL_A4
    PMOD2(2) <= '0'; -- cathode 4 SEG_CTRL_L?
    PMOD3(6) <= sseg_edu_anode_out(0); --A SSEG0_A
    PMOD3(5) <= sseg_edu_anode_out(1); --B SSEG1_B
    PMOD3(3) <= sseg_edu_anode_out(2); --C SSEG2_C
    PMOD2(6) <= sseg_edu_anode_out(3); --D SSEG3_D
    PMOD2(7) <= sseg_edu_anode_out(4); --E SSEG4_E
    PMOD3(7) <= sseg_edu_anode_out(5); --F SSEG5_F
    PMOD3(2) <= sseg_edu_anode_out(6); --G SSEG6_G
    PMOD3(4) <= sseg_edu_anode_out(7); --DP SSEG7_DP

3 Missing files: logi_edu_test.xise

vga_bar_top.vhd,
vga_sync.vhd

logi_edu_test.xise point both these files as in local directory,
both should be: ../hdl/

wishbone_7seg4x.vhd
found in fpga-logi-dev
https://github.com/fpga-logi-dev/logi-hard/blob/master/hdl/wishbone/peripherals/

logipi_wishbone: clock_gen missing

tried to synthesize:

WARNING:ProjectMgmt - File /ipcore_dir/clock_gen/example_design/clock_gen_exdes.ucf is missing.
WARNING:ProjectMgmt - File /ipcore_dir/clock_gen/example_design/clock_gen_exdes.vhd is missing.

logi-wishbone infos and ucf file

Hello all,
I am new on LogiBone so i am trying the examples. I want to study wishbone communication.
I tried the wishbone project from the LogiBone and it worked.

Now i am trying to create the .bit file from the logibone-wishbone.xise.
When i opened the project it was asking for gpmc2wishbone - gpmc_wishbone_wrapper. I found the file in logi-hard-master.
The project now makes the .bit file but in my LogiBone the Led does not operates as in the predefined example.

My question is (i am sorry if it is a silly question) there is no .ucf file in the project. Do i have to include a .ucf file?
I tried with different .ucf files from the logi-hard-master folder but when i try to compile the project i get these errors:

1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

Also i want to ask which the max speed that i can get data at the BeagleBoneBlack from the LogiBone through wishbone?

Thank you very much,
George

logi-wishbone: missing synchronizers in gpmc_wishbone_wrapper?

Hi experts,

I am trying to get familiar with the Logibone studying the logi-wishbone project. In the gpmc_wishbone_wrapper module there is a clock domain crossing between the GPMC and the Wishbone, but the destination domain only presents a single FF before the signals are sent to the Wishbone interconnect network. Should not it use a dual FF synchronizer to avoid metastability?

In the same file, the attribute IOB of iob_writedata is set to true. After reading Xilinx documentation, I understand that this attribute is used to pull a register into an IOB cell, but iob_writedata is not a registered signal (it connects directly to the three-state buffer in the IO pad). Should not the attribute apply to a registered signal to have any effect?

I apologize if my comments are not issues at all. I am not an expert in hardware design and sometimes I find Xilinx documentation overwhelming (even confusing), so I might miss some details.

Thank you,
JC

rpi2+1.5.1 logi board bitcoin_app never ends

Only output:

[0, 0, 0, 0]

About one line/5 seconds. Once on start I got nonce ffffffff immediately then exit.

After a bit of googling I did find a beaglebone reference that said it'd take 2 min. I've been waiting for hours.

LED1 is blinking ~2 times/sec.

Thanks.