fserre/sgen

SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset is divided into several chunks that are processed during several cycles, thus allowing a reduced use of resources. The size of these chunks is referred as the streaming width. It outputs a Verilog file that can be used for FPGAs.

sgen's Issues

Huge Memory Use

When used for FFT with n = 10 and k=7, complex char data type, the memory usage is superior to 128Gb. Is it a feature?
...
[info] running main -n 10 -k 7 -r 1 -hw complex fixedpoint 4 4 dft
...
[error] (run-main-0) java.lang.IllegalArgumentException: requirement failed: ArrayDeque too big - cannot allocate ArrayDeque of length 1073741824
...

Mismatch between expected output and actual output when running testbench

Hi there,
I was running the testbench for the design of 65536-point FFT with 256 streaming width. In terms of fixed-point representation, I set 8-bit integer and 8-bit fraction. Under this setting, I encountered the case that the actual output is mismatched with the expected output. I have seen the output of some points are really close to the expected output, while some have a large gap. I would like to know if this case is normal and if this is due to the precision loss of fixed-point representation. Below, I capture part of the testbench output. I would really appreciate a quick response.

Add support for inverse FFT and scaled-down FFT

Add option to control FFT twiddles precision

Add a i_valid for slow inputs (high system_clk/sample_clk ratios)

Waste of extra BRAM or other resources to keep feeding the core k samples every cycle if the input data rate is much slower than system clock (which dftcompact/burst is perfect for). The same thing with the output, the blocks downstream likely can't keep up with k samples every clock cycle. valid signal will improve usability greatly, ready too can help with signaling end of dataset.

Request for testbench

Hi,

I'm a hardware designer looking for some available fft core in verilog or vhdl and find out your great contribution here. But this repo does not seem to be complete. There is no testbench for the generated fft core nor other program for testing the fft core. The README is not enough to be a document for the whole program.

Maybe the author could add some testbench or some documents to make the project more complete.

Add Chisel backend

DFT generation with 1 sample per cycle fails

I changed the project version from 1.5.5 to 1.8.0 to get around a Java issue like this related to sbt not starting:
sbt/sbt#6925

Now the generator runs, but not if I select n=6, k=0 (1 sample per cycle). With n=6, k=1 it works fine. Or with n=6, k=6 it also works fine. See below for the NoSuchElementException:

sbt "run -n 6 -k 0 -hw complex fixedpoint 16 0 -dualramcontrol -o sgen_dft.v dft"
[info] welcome to sbt 1.8.0 (Homebrew Java 19.0.1)
[info] loading project definition from /Users/<user>/git/SGen/project
[info] loading settings for project root from build.sbt ...
[info] set current project to SGen (in build file:/Users/<user>/git/SGen/)
[info] running (fork) Main -n 6 -k 0 -hw complex fixedpoint 16 0 -dualramcontrol -o sgen_dft.v dft
[info]    _____ ______          SGen v.0.2 - A Generator of Streaming Hardware
[info]   / ___// ____/__  ____  Department of Computer Science, ETH Zurich, Switzerland
[info]   \__ \/ / __/ _ \/ __ \
[info]  ___/ / /_/ /  __/ / / / Copyright (C) 2020-2021 François Serre ([email protected])
[info] /____/\____/\___/_/ /_/  https://github.com/fserre/sgen
[info] This program comes with ABSOLUTELY NO WARRANTY. This is free software, and you are welcome to redistribute it and to modify it under the terms of the GNU GPLv3+ <http://gnu.org/licenses/gpl.html>.
[error] Exception in thread "main" java.util.NoSuchElementException: empty.head
[error] 	at scala.collection.immutable.Vector.head(Vector.scala:277)
[error] 	at Main$.r$1(Main.scala:62)
[error] 	at Main$.main(Main.scala:153)
[error] 	at Main.main(Main.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / run) Nonzero exit code returned from runner: 1
[error] Total time: 1 s, completed Dec 12, 2022, 3:17:50 PM

Bad Coding Style

Bad coding style of combinatorial logic using non-blocking assignment