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Development board for Lattice Crosslink-NX 72QFN
In-line resistors on high speed banks leading to the PMODs prohibit use of these pins for ~gigabit speed signals.
Solutions:
These design choices result in the LED activating from the ~1.5V that is applied across it and the current drawn from the weak-pull ups. Because LEDs are so efficient the LED appears around 50% brightness in this condition.
While IDLE the FTDI appears to drive the bus reasonably hard. Enough to result in signals only making it to around 1/2 Vcc when driven by the FPGA. Because the FTDI is a second master connected to the FLASH for programming. This results in the configuration not being correctly loaded by the FPGA.
Adding 100R resistance inline to the following signals is enough to weaken the FTDIs grasp.
PSRAM is available in standard SOIC8 packages, the hardware is populated with a Wide SOIC8 footprint.
The RAM still fits well enough.
Severity: minor.
It had to be said :)
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