Comments (7)
from hdmi.
Please give https://github.com/hdl-util/hdmi/tree/v1.2.1-verilog a try. I've converted to Verilog using sv2v and made sure it can compile.
Let me know if you run into any problems!
from hdmi.
Thanks a lot! I'm on it right now!
After solving small issues (mixing of blocking and non-blocking assignments) and the problem of $clog2 in localparams...
I'm trying to solve the serializer (not posible in Verilog assign both on rise and fall edges)
Let's see if I can use the IP instantiated version of the SV code.
from hdmi.
from hdmi.
Sorry for taking so long. Bad news! I've tried several ways but can't get any HDMI image. I've solved som issues due the translation, and even used other serializers with the Spartan6 primitives.
As result: a few warnings, all signals routed, all constraints met, perfect timing report and bitfile created; but no image or sound.
I give up. Thanks a lot for your effort!
from hdmi.
from hdmi.
Sure! Thanks a lot!
https://github.com/TheSonders/Hdmi
from hdmi.
Related Issues (20)
- LCD Bus Compatible Input HOT 4
- Casting that is used in testbench is not in accordance with LRM HOT 1
- Works on ULX3S (Lattice ECP5) HOT 13
- sawtooth sound output problem HOT 7
- something wrong in audio HOT 6
- implmenting hdl-util/hdmi on a Spartan Edge Accelerator system HOT 1
- Tang Nano 9K HOT 3
- Need help... HOT 19
- Not apply
- IP-less serializer is not working HOT 1
- Source Product Description Infoframe checksum wrong HOT 1
- Distorted audio when 24bits are used HOT 1
- Can't Synthesis on Vivado 2022 HOT 1
- Incorrect Calculation Formula for N in Audio Regeneration HOT 1
- Potential violation of the HDMI 12 pixel minimum control period HOT 4
- Clarify license HOT 2
- DDR instead of LVDS output. HOT 1
- some information HOT 2
- incompatibility with capture devices HOT 2
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from hdmi.