Need help...

[hdl-util]

Need help...

[edanuff]

Thought the problem was in the control data component but on second look, I don't think that's the problem.

[edanuff]

Hi Sameer, DVI_OUTPUT(1) fixes the problem with the Eizo monitors (both the previous version and the current version).

However, it doesn't fix the issue I'm seeing with the Eyoyo HDMI monitor that I'm also using for testing. WIth that monitor, what I see with both the previous version and the #44 fix is:

hdl-util/hdmi with DVI_OUTPUT(0): works
SimpleVOut: works
hdl-util/hdmi with DVI_OUTPUT(1): blank screen except after about a minute or two it then works

[sameer]

I am surprised you are actually able to see the guard bands... that implies that the sink is understanding the hdmi input and the guard is somehow duplicated. I feel like there could be some hardware setup / parameter issue.

Few more questions:

• What FPGA board are you using?
• Have you tried alternate HDMI cables?
• Is the HDMI port on the board or did you solder it yourself?
• Can you share the parameters you used when instantiating the hdmi module?

[mopplayer]

Hi @sameer,

The guardband is like author (https://github.com/charcole/NeoGeoHDMI/blob/master/HDMIDirect.v) saying.

		// Send the data period preamble
		// A nice "feature" of my test monitor (GL2450) is if you comment out
		// this line you see your data next to your image which is useful for
		// debugging

If I change this `define VIDEO_GUARDBAND 32
I get this for fun:
https://imgur.com/1vVq5b5

What FPGA board are you using?
My board is Lichee Tang Primer. The FPGA is Anlogic EG4S20.
But if it works under DVI mode only, that video guard band also disappears, anything is fine.
I want the audio working.
If only I use this repo to do, there is no signal (720x480, 59.94, 27M, 32K for both monitors)

Have you tried alternate HDMI cables?
Changing cables is the same result.

Is the HDMI port on the board or did you solder it yourself?
The HDMI port is connected between 2.54 pins and wires (21 cm). Port setting is LVDS3V3.

Can you share the parameters you used when instantiating the hdmi module?

I am based on charcole code: Other settings in the code leaving no changes. (720 x 480, N=4096, CTS=27000, and so on)
You could just see the main block (https://github.com/charcole/NeoGeoHDMI/blob/8d66141d150ea53abcc77258ed8db8890887f646/HDMIDirect.v#L642)

HDMIDirectV	u_HDMIDirectV(
	.pclk_hdmix5(pclk_hdmix5),	
	.pclk_hdmi(pclk_hdmi),		
	.reset(reset),
	.red(red),		
	.green(green),
	.blue(blue),					
	.CounterX(CounterX),	
	.CounterY(CounterY),		
	.audioL(audioL),			
	.audioR(audioR),		
	.TMDS(TMDS),		
	.led(led)
); 		 

[sameer]

I mean the module parameters for this repo, i.e. VIDEO_ID_CODE. Unfortunately, I don't have the bandwidth to look into the charcole code.

Lichee Tang Primer

I recently got the Tang Nano 9k and I'm planning to set up a demo in hdi-util/hdmi-demo for it. Will let you know if I run into similar issues with it

[mopplayer]

Hi @sameer,

VIDEO_ID_CODE = 2, other setting is listed above.
That's OK, just see your repo and code, Now there is no signal.

hdmi #(.VIDEO_ID_CODE(2), .VIDEO_REFRESH_RATE(59.94), .AUDIO_RATE(32000), .AUDIO_BIT_WIDTH(16)) hdmi(

And you could check the difference from waveform:
The serializer is totally same.
Your repo:
https://imgur.com/0GJqTCT

others:
https://imgur.com/j5k7RjA

I also notice that "LVDS voltage swing range from 250mV(minimum) to 450mV (maximum) with a typical value of 350mV. Because the voltage swing is very low and."

So..., it might be the electrical  problem, need several resistors to lower the peak-peak.

By now, I connect directly to the HDMI connector from the FPGA LVDS33 pin.

Thank you very much.

[mopplayer]

Congratulations!

I could hear the sounds using the  charcole code.

And the video guard band disappeared.

But I do not know why....

Now I use "emulated" LVDS33 (i.e. not true LVDS33) to send TMDS signal.

From the manual, emulated LVDS33 needs some external resistors to low down swing voltage....

But I connect directly to the HDMI connector.

You could see the waveform and peak-peak.

TMDS:
https://imgur.com/L70d2X0

TMDS clock:
https://imgur.com/QBM55jl

Did you know why?

By the way,  your repo and code still have no signal....
https://imgur.com/AlrFEhf

[hvegh]

Hi all, would like to share my findings with Tang Nano 9K:

On my older Samsung TV audio and video work on the port labeled "HDMI/DVI" the other HDMI port on this device has no output.
The newer Samsung TV I have, knows there is a device but fails with check cables on all of the HDMI ports... so no output here.

So I think maybe mode line is not supported i check:

Linux report on TV:

// Modeline "Mode 4" 74.250 1280  1390       1420     1650   720   725        730      750 +hsync +vsync
//                   pclk   hdisp hsyncstart hsyncend htotal vdisp vsyncstart vsyncend vtotal

So slight adjustment in the hdmi.v table changed the hsync_pulse_size to 30 in order to match modeline...

        4:
        begin
            assign screen_width      = 1280;
            assign hsync_pulse_start = 110;
            assign hsync_pulse_size  = 30; // 40;
            assign frame_width       = 1650;

            assign screen_height     = 720;
            assign vsync_pulse_start = 5;
            assign vsync_pulse_size  = 5;
            assign frame_height      = 750;
            assign invert            = 0;
        end

Still no luck, any ideas?

Kind regards,
Henk

[hvegh]

So questions is:

Why do regular TV's not support this signal.
While DVI monitors output this signal without problem...

Is it electrical compatibility?
For Gowin I use emulated LVDS ...

Or is it some sort of configuration issue where the TV decides the content is not compliant, due to not being encrypted?

[edanuff]

Old open issue, but seeing related problem with Tang Nano 9k - testing with Eizo monitors that work with the SimpleVOut core that Sipeed uses in their demos (picotiny, etc.), but finding do not work when using this core, even with same resolutions and clock timing.

[sameer]

Old open issue, but seeing related problem with Tang Nano 9k - testing with Eizo monitors that work with the SimpleVOut core that Sipeed uses in their demos (picotiny, etc.), but finding do not work when using this core, even with same resolutions and clock timing.

From what I can tell, SimpleVOut is just a DVI signal. It is possible that those monitors do not support true HDMI, could you try setting DVI_OUTPUT to 1? https://github.com/hdl-util/hdmi/blob/master/src/hdmi.sv#L30

That will help pinpoint things further.

@edanuff

[sameer]

Also, I see that you started a Tang Nano 9k demo -- if you get it working would really love to see it merged into https://github.com/hdl-util/hdmi-demo

[edanuff]

Hi Sameer, thanks for your reply. I was looking at the DVI_OUTPUT flag but when I turn that on, it stops working on my HDMI monitors. This original problem I'm trying to solve is that I'm using your HDMI core in a different Tang Nano 9K project and I got a bug report by one of my testers that it wasn't working with either of his Eizo monitors. After discussing with him and looking at the spec sheets for the monitors, it became clear these monitors were DVI monitors being used with an HDMI adapter. I was going to do a build with DVI_OUTPUT set to 1 and see if it fixes it for him but I was trying to figure out why DVI_OUTPUT didn't work with my HDMI monitors first. I'll also clean up the hdmi-demo example and send it as a pull request. That was just a mashup of Sipeed's HDMI example and your hdmi-demo code.

EDIT: DVI_OUTPUT=1 causes it to stop working on one of my HDMI monitors, interestingly SimpleVOut does work on this monitor though. I will update once I've determined with DVI_OUTPUT=1 fixes the problem on the actual DVI monitors.

[sameer]

EDIT: DVI_OUTPUT=1 causes it to stop working on one of my HDMI monitors, interestingly SimpleVOut does work on this monitor though. I will update once I've determined with DVI_OUTPUT=1 fixes the problem on the actual DVI monitors.

That's definitely not expected, thank you for looking into it!

[sameer]

It's possible we may need some more configuration than just DVI_OUTPUT. Maybe the data islands are not supported by these DVI sinks, but some of the other stuff like the guard bands can go unignored.

[sameer]

@edanuff would you mind checking if this is fixed by #44?

[krisdover]

hdl-util/hdmi with DVI_OUTPUT(0): works SimpleVOut: works hdl-util/hdmi with DVI_OUTPUT(1): blank screen except after about a minute or two it then works

@sameer I wonder if this might have something to do with legacy DVI having a different TMDS encoding for control data. Page 29 of the DVI v1.0 spec has the following:

Also have a look at how legacy TMDS encoding is handled in this video lag tester project I've been tinkering with. Hope this helps.

[xtreme8000]

I wonder if this might have something to do with legacy DVI having a different TMDS encoding for control data. Page 29 of the DVI v1.0 spec has the following

@krisdover I just came here from google; the control data encoding is in fact the same for HDMI and DVI, it's just that the bits are written mirrored in the DVI spec. Note how it says q_out[0:9] there vs q_out[9:0] in 5.4.2 of the HDMI 1.4 spec.

[krisdover]

@xtreme8000 ah, I did not realise that was the only difference. Thanks for clarifying.