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arm_m3_design

personal practice

arm_soc

ARM Cortex-M0 design start SoC

automatic-verilog_gvim

automatic-verilog-vimscript

awesome

A curated list of awesome resources for HDL design and verification

awesome-books

技术类精华书单推荐，包括 前端、后端、数据结构与算法、计算机基础、设计模式、数据库等书籍。

awesome-cheatsheets-vim-

超级速查表 - 编程语言、框架和开发工具的速查表，单个文件包含一切你需要知道的东西 :zap:

awesome-courses

:books: List of awesome university courses for learning Computer Science!

awesome-cpp

A curated list of awesome C++ (or C) frameworks, libraries, resources, and shiny things. Inspired by awesome-... stuff.

awesome-dv

Awesome ASIC design verification

awesome-eda

awesome-fpga

A collection of resources on FPGA devices and development in general

awesome-functional-verification

list of links to resources related to functional verification

awesome-hwd-tools

A curated list of awesome open source hardware design tools

awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

awesome-opensource-asic-resources

awesomescripts

A Collection of Awesome Scripts in Python to Ease Daily-Life. Create an issue If you have some great ideas for the new script. Leave a :star:

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

axi

AXI4 and AXI4-Lite interface definitions and testbench utilities

axi-uvm

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

axi4_master

Custom axi4 master

axi4_vip

Verification IP for APB protocol

barebonescortexm0

Extremely basic CortexM0 SoC based on ARM DesignStart Eval

batchrun

batchRun is an ansible-similar IT automation system, which is more suitable for IC industry.

best-coding-practices-

Describes the best coding practices and guidelines

biriscv

32-bit Superscalar RISC-V CPU

black-parrot

A Linux-capable RISC-V multicore for and by the world

cagt

Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast an UVM based agent for any protocol.

caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

caravel_user_project_analog

clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler