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sm3_core

soc-dv

System on Chip verified with UVM/OSVVM/FV

soc-freedom-sifive

e300 and u500 devkits

soc-riscv

System on Chip with RISCV-32 / RISCV-64 / RISCV-128

soc_automation

SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.

srcery-vim

Dark colorscheme for gvim and vim

surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

sv-parser

SystemVerilog parser library fully complient with IEEE 1800-2017

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

svaunit

SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)

svaunit_sandbox

Example code for "A Quick Look at SVAunit" post

svlib

svlib from http://www.verilab.com/resources/svlib/

svls

SystemVerilog language server

svmock

A mock framework for use with SVUnit

svunit

swd_iap

ARM内核简易烧录装置

swd_programing_sram

Programming internal SRAM over ARM Cortex M3 SWD

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

systemverilog-design-patterns

systemverilog-uart16550

SystemVerilog uart16550

systemverilog_design_pattern

The source code of blog

teachyourselfcs-cn

TeachYourselfCS 的中文翻译 | A Chinese translation of TeachYourselfCS

test

项目描述

testing_seqs_and_props

testing_uvm_drivers

Example code for "Testing UVM Drivers"

testing_uvm_drivers_pt2

Example code for "Testing UVM Drivers, Part 2" post

tgen

Test list generator

the-project-of-verilog

Some design examples of Verilog about digital circuits

timer_unit

tinyriscv

A very simple and easy to understand RISC-V core.