himanshushah05/vlsi_design_multipliers

This repository holds some different architectures for multipliers which have been used alongwith verilog code and testbench as well.

VLSIdesign_multipliers

Different Multiplier Archetectures

Getting started 👇

• pull any design file you like to execute and also pull the respective testbench file
• These designs can be simulated using any of the following tools or softwares:
  • EDA tool - This is an online tool
  • Vivado Xilinx
  • Intel Modelsim

Understanding different types of multipliers 📜

1. Carray Save Array Multiplier : csa_4bit.v

• This architecture supports unsigned numbers only.
• In this type of architecture, the carry is passed to the next column and next row.
• This helps in reducing the delay of the circuit.

2. 4-Bit Bough-Wooley Array Multiplier Design : sma_signed.v

• This architecture supports signed numbers also.
• It is a signed multiplier which follows 2’s compliment arithmetic.

3. Wallace-Tree Multiplier : wallace_4bit.v

• This architecture supports unsigned numbers only.
• In this type of architecture, we try to perform the partial products as quickly as possible.
• This architecture is more suitable and time saving for n>8, where n is number of bits.
• In this architecture, the number of half-adders and full-adders is more.

4. Dadda-Tree multiplier : dadda_mul_4bit.v

• This architecture supports unsigned numbers only
• In this type of architecture, we perform the partial product as late as possible.
• This architecture has lesser number of half-adders and full-adders.
• This architecture has longest path in the final adder

If compared to Wallace tree multiplier, Dadda tree multiplier has an advantage of lesser area but a disadvantage of more delay time.

5. Squarer circuit : square_4bit.v

• We think, squarer circuit is same as multiplier, but it is not, squarer circuit is much more simplified and fast (in terms of delay)
• Such squarer circuits are used in almost every DSP algorithm.