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Out-of-Order processor design

Home Page: http://code.google.com/p/mountain-dew-proc/

Makefile 0.48% Elixir 0.18% Rust 0.17% Perl 0.43% Shell 0.87% Tcl 4.57% SystemVerilog 1.22% Verilog 35.69% C 7.28% Assembly 49.11%

eecs470-proc's Introduction

README for EECS 470 W11 Group 4

1) a)  Run Simulation - make simv
       Run Synthesis  - make syn
       Run in Debug   - make DEBUG=1 [simv|syn]
       Run all tests and compare against in order processor: run_tests.sh --help
            Read help for more details, requires an in-order
            processor to compare against (to compare memory,
            inorder needs to output memory to memory.out)
   b)  synth/oo_pipeline.out
       synth/oo_pipeline.rep
       synth/pipeline.vg
   c)  Final clock period is 7.7ns
   d)  All tests in test_progs report same results as in order processor.
       Therefore all tests pass.


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