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License: MIT License
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
License: MIT License
Hi,
Do you guys have any reports related to coverage of your verification infrastructure? In other words, how good/mature is your verification environment?
Thanks!
We need a DDR4 Controller, to manage global memory, which sits in DDR chips, separate from the main GPU chip.
The DDR4 Controller will be used to copy data to and from the GPU global memory, in order to populate shared memory, caches and similar on the GPU chip itself; and in order for the GPU to be able to write data back to global memory. For now, we will assume that all communications are with a single GPU Controller module on the GPU die. For example, we will assume for now that any data copied from mainboard main memory to GPU global memory will pass via the GPU controller.
What we need for VeriGPU:
Bear in mind that tape-out at 5nm costs $250M or so, so we want things to work first time. Therefore verification is important :)
Hello, I'm having troubles in building the project, as the documentation is not that clear.
What is happening is that during the exec of the CMake verilate command, the flag "--make" is not found, hence it doesn't create further .cmake files (e.g., gpu_card_copy.cmake).
Is this issue related to the version of Verilator being used? If so, could you please tell which version of Verilator are you using? Thanks.
Does anyone have an understanding into the trade-offs of providing an instruction point to each core, or only to each computer unit?
Things that occur to me, in favor of only having a single program counter per compute unit:
On the other hand, in favor of separate program counters in each core:
if
statements, and branching: each thread just executes what it needs to execute. no need for all threads to execute an if
block that only one thread actually needs, and then throwing away their resultsHey,
I want to implement this thing in VAAMAN, ( https://vicharak.in/vaaman ),
I can dedicate few 2-3 persons full time to it. But i need some documentation to understand architecture.
Thanks
Have you considered doing a tape out of your VeriGPU using the SKY130 PDK and no-cost shuttle program?
My team launched the fully open source 130nm PDK with SkyWater (http://github.com/google/skywater-pdk) with a no-cost shuttle program (https://efabless.com/open_shuttle_program). You can see more information from my talk at ESSCIRC/ESSDERC last year, see slides @ https://j.mp/esscxxrc21-sky130 and the recording recording @ https://j.mp/esscxxrc21-sky130-video
While 10mm2 might be a bit small for a GPU, it could still be used to test a lot of interesting parts. Things like DFFRAM (https://github.com/Cloud-V/DFFRAM) can be used for optimizing things like the register file.
Hi, I got some error message during make gpu runtime.
error: ‘class llvm::ElementCount’ has no member named ‘getFixedValue’
int elementCount = vectorType->getElementCount().getFixedValue();
The environment is ubuntu20 with clang 10.
@hughperkins @hpasapp hi there is this hardware gpu or only scripts for software.
thanks
This way all software can be reused.
And if possible, make this RVV1.0 ready will be really interesting.
Hi, I am adding some more direct test ASMs to the project so xxxx_expected.txt should also be added.
I'd like to know, how the files in "examples/direct/expected" are generated? I didn't see any info about this in docs.
Hi, I'm trying to add some FVs on the current design, is there any cmodel/golden?
Need a PCIe 4+ interface, for communications between the main computer's CPUs, and the GPU board.
The PCIe interface will be used to copy data to and from the mainboard memory; to receive kernel launch requests from a mainboard CPU core; and to inform the mainboard CPU core once the kernel has finished running.
What we need for VeriGPU:
Introduction to PCIe https://pcisig.com/sites/default/files/files/PCI_Express_Basics_Background.pdf
(from linked presentation)
Bear in mind that taping out at 5nm costs $250M or so, so we want things to work first time. Therefore verification is important :)
There are 31 registers, x1 to x31, along with x0, which is always 0s. Use the same registers for both integers and floats. (this latter point deviates from RISC-V, because we are targeting creating a GPU, where locality is based around each of thousands of tiny cores, rather than around the FP unit vs the integer APU).
RISC-V has the "Zfinx" extension, specifically for this. So if you follow that then you're not deviating.
https://github.com/riscv/riscv-zfinx
What else?
Need a network on a chip implementation
Firstly, what is network on a chip? See https://amstel.estec.esa.int/tecedm/NoC_workshop/GinosarNOC_Tutorial.pdf Buses are becoming spaghetti, so chips nowadays use an internal packet-switching network instead.
(slide from presentation linked above)Then the tasks for NoC for VeriGPU are:
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