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Wrappers for open source FPU hardware implementations.

License: MIT License

Scala 0.50% Tcl 0.01% Python 0.03% Verilog 99.33% SystemVerilog 0.12% Makefile 0.01% Nix 0.01%
fpu hdl chisel3 spinalhdl

fpu-wrappers's Introduction

fpu-wrappers

This repo intends to create wrappers for open source FPU hardware implementations currently including:

  1. berkeley-hardfloat
  2. fpnew
  3. flopoco
  4. CNRV-FPU
  5. opencores-fpu
  6. fudian
  7. vfloat
op berkeley-hardfloat fpnew flopoco CNRV-FPU opencores-fpu fudian vfloat
add Y Y Y Y Y Y Y
mul Y Y Y Y Y Y Y
fma Y Y Y Y Y Y
cmp Y Y Y Y
div Y Y Y Y Y Y Y
sqrt Y Y Y Y Y Y
fp2int Y Y Y Y Y Y Y
int2fp Y Y Y Y Y Y Y
fp2fp Y Y Y Y
pow Y
log Y
exp Y
custom Y Y

custom means custom floating point format.

And make performance comparison.

Module naming convection:

  1. Type 1: Floating point format + operator(FAdd/FMA/FExp)
  2. Type 2: Floating point format To Floating point format
  3. Type 3: Floating point format + FPU(many operations)

Possible floating point formats:

  1. HF: berkeley-hardfloat +1 bits
  2. IEEE: IEEE 754
  3. FPC: flopoco +2 bits

IEEE754 FMA:

  1. Area: fpnew = flopoco < hardfloat < fudian
  2. Frequency: hardfloat = flopoco > fpnew > fudian
  3. Power: fpnew < hardfloat < flopoco < fudian

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