joel-dandin / vivado-risc-v Goto Github PK

This project forked from eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Shell 0.07% C++ 0.01% Python 0.08% C 36.13% Java 17.61% Scala 0.43% Tcl 41.16% VHDL 0.38% Verilog 3.09% Assembly 0.01% ANTLR 0.72% Makefile 0.31%

boom fpga genesys2 kc705 linux nexys nexys-a7 nexys-video risc-v riscv riscv64 rocketchip vc707

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