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FPGA board support and core ports for MiSTeX

License: BSD 3-Clause "New" or "Revised" License

Shell 0.01% Python 2.88% C 0.67% Tcl 5.01% VHDL 27.66% Verilog 48.21% SystemVerilog 15.56%

mistex-ports's Introduction

MiSTeX

Usage example for Menu core:

echo export PATH="/opt/intelFPGA_lite/17.1/quartus/bin:$PATH"
# python3 [path_to_board_definition.py] [core_name]
python3 mistex_boards/terasic_deca_retro_cape.py Menu

Note: You can use an up to date quartus for Intel based development boards, unlike MiSTer. For Xilinx based boards, you need a recent Vivado version installed.

You will need to have the LiteX python packages installed though pip3 install litex and follow LiteX installation guide from https://github.com/enjoy-digital/litex/wiki/Installation

mistex-ports's People

Contributors

hansfbaier avatar darfpga avatar somhi avatar mjoergen avatar

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