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View Code? Open in Web Editor NEWFPGA board support and core ports for MiSTeX
License: BSD 3-Clause "New" or "Revised" License
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No module named 'litedram'
While running qmtech_xc7a100t_daughterboard.py script for my QMTech xc7a110t board, I have got:
MiSTeX-boards/mistex_boards main ./qmtech_xc7a100t_daughterboard.py
Traceback (most recent call last):
File "/home/chandler/Documentos/MiSTeX-boards/mistex_boards/./qmtech_xc7a100t_daughterboard.py", line 30, in <module>
from litedram.modules import MT41J128M16
ModuleNotFoundError: No module named 'litedram'
Procedure done:
- Installed python and needed packages
- git clone
MiSTeX-boardsrepo cd MiSTeX-boards/mistex_boards./qmtech_xc7a100t_daughterboard.py
System and Python Interpreter:
$ uname -r
6.3.7-arch1-1
$ python --version
Python 3.11.3
Packages used:
migen
Name: migen
Version: 0.9.2
Summary: Python toolbox for building complex digital hardware
Home-page: https://m-labs.hk
Author: Sebastien Bourdeauducq
Author-email: [email protected]
License: BSD
Location: /home/chandler/.local/lib/python3.11/site-packages
Requires: colorama
Required-by: litex
litex
Name: litex
Version: 2023.4
Summary: Python SoC/Core builder for building FPGA based systems.
Home-page: http://enjoy-digital.fr
Author: Florent Kermarrec
Author-email: [email protected]
License: BSD
Location: /home/chandler/.local/lib/python3.11/site-packages
Requires: migen, packaging, pyserial, requests
Required-by:
litex-boards
Name: litex-boards
Version: 0.0.0
Summary: LiteX supported boards
Home-page: http://enjoy-digital.fr
Author: Florent Kermarrec
Author-email: [email protected]
License: BSD
Location: /home/chandler/.local/lib/python3.11/site-packages
Requires:
Required-by:
test
<style>
.basic-styling td,
.basic-styling th {
border: 1px solid #999;
padding: 0.5rem;
}
</style>
Table 6:
Table with uncollapsed borders
| Name | ID | Favorite Color |
|---|---|---|
| Jim | 00001 | Blue |
| Sue | 00002 | Red |
| Barb | 00003 | Green |
identifier "btn_*" is already declared in the present scope
Problem:
Buillding Menu core throws error for double declarations.
Log:
--- SNIP ---
Info (12021): Found 3 design units, including 3 entities, in source file /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/math.sv
Info (12023): Found entity 1: sys_udiv File: /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/math.sv Line: 3
Info (12023): Found entity 2: sys_umul File: /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/math.sv Line: 46
Info (12023): Found entity 3: sys_umuldiv File: /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/math.sv Line: 85
Error (10149): Verilog HDL Declaration error at sys_top.v(291): identifier "btn_r" is already declared in the present scope File: /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/sys_top.v Line: 291
Error (10149): Verilog HDL Declaration error at sys_top.v(292): identifier "btn_o" is already declared in the present scope File: /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/sys_top.v Line: 292
Error (10149): Verilog HDL Declaration error at sys_top.v(293): identifier "btn_u" is already declared in the present scope File: /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/sys_top.v Line: 293
Error (10112): Ignored design unit "sys_top" at sys_top.v(22) due to previous errors File: /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/sys_top.v Line: 22
Error (10112): Ignored design unit "sync_fix" at sys_top.v(1910) due to previous errors File: /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/sys_top.v Line: 1910
Error (10112): Ignored design unit "csync" at sys_top.v(1942) due to previous errors File: /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/sys_top.v Line: 1942
Info (12021): Found 0 design units, including 0 entities, in source file /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/sys_top.v
Info (12021): Found 1 design units, including 1 entities, in source file /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/scandoubler.v
Info (12023): Found entity 1: scandoubler File: /home/dev/Code/MiSTeX-devel/MiSTeX-boards/cores/Template/sys/scandoubler.v Line: 22
--- SNIP ---
Info (144001): Generated suppressed messages file /home/dev/Code/MiSTeX-devel/MiSTeX-boards/build/qmtech_ep4cgx150_mistex/Menu/Menu_MiSTeX.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 6 errors, 5 warnings
Error: Peak virtual memory: 485 megabytes
Error: Processing ended: Fri Apr 12 09:07:57 2024
Error: Elapsed time: 00:00:07
Error: Total CPU time (on all processors): 00:00:17
Traceback (most recent call last):
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/mistex_boards/qmtech_ep4cgx150_mistex.py", line 297, in
handle_main(main)
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/mistex_boards/util.py", line 183, in handle_main
main(coredir, core)
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/mistex_boards/qmtech_ep4cgx150_mistex.py", line 294, in main
builder.build(build_name = get_build_name(core))
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/venv/lib/python3.10/site-packages/litex/soc/integration/builder.py", line 370, in build
vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/venv/lib/python3.10/site-packages/litex/soc/integration/soc.py", line 1383, in build
return self.platform.build(self, *args, **kwargs)
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/venv/lib/python3.10/site-packages/litex/build/altera/platform.py", line 45, in build
return self.toolchain.build(self, *args, **kwargs)
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/venv/lib/python3.10/site-packages/litex/build/generic_toolchain.py", line 123, in build
self.run_script(script)
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/venv/lib/python3.10/site-packages/litex/build/altera/quartus.py", line 216, in run_script
raise OSError("Error occured during Quartus's script execution.")
OSError: Error occured during Quartus's script execution.
ERROR: Could not detect Ninja v1.8.2 or newer
Problem:
ninja is not installed in venv.
Log:
--- SNIP --
Configuring picolibc.h using configuration
Build targets in project: 9
NOTICE: Future-deprecated features used:
- 0.56.0: {'meson.source_root'}
- 0.58.0: {'meson.get_cross_property'}
picolibc 1.7.9
User defined options
Cross files : cross.txt
includedir : picolibc/riscv64-unknown-elf/include
libdir : picolibc/riscv64-unknown-elf/lib
atomic-ungetc : false
format-default : integer
io-long-long : true
multilib : false
picocrt : false
thread-local-storage: false
ERROR: Could not detect Ninja v1.8.2 or newer
A full log can be found at /home/dev/Code/MiSTeX-devel/MiSTeX-boards/build/qmtech_ep4cgx150_mistex/Menu/software/libc/meson-logs/meson-log.txt
make: *** [/home/dev/Code/MiSTeX-devel/MiSTeX-boards/venv/lib/python3.10/site-packages/litex/soc/software/libc/Makefile:43: __libc.a] Error 1
make: Leaving directory '/home/dev/Code/MiSTeX-devel/MiSTeX-boards/build/qmtech_ep4cgx150_mistex/Menu/software/libc'
Traceback (most recent call last):
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/mistex_boards/qmtech_ep4cgx150_mistex.py", line 297, in
handle_main(main)
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/mistex_boards/util.py", line 183, in handle_main
main(coredir, core)
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/mistex_boards/qmtech_ep4cgx150_mistex.py", line 294, in main
builder.build(build_name = get_build_name(core))
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/venv/lib/python3.10/site-packages/litex/soc/integration/builder.py", line 357, in build
self._generate_rom_software(compile_bios=use_bios)
File "/home/dev/Code/MiSTeX-devel/MiSTeX-boards/venv/lib/python3.10/site-packages/litex/soc/integration/builder.py", line 291, in _generate_rom_software
subprocess.check_call(["make", "-C", dst_dir, "-f", makefile])
File "/usr/lib/python3.10/subprocess.py", line 369, in check_call
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['make', '-C', '/home/dev/Code/MiSTeX-devel/MiSTeX-boards/build/qmtech_ep4cgx150_mistex/Menu/software/libc', '-f', '/home/dev/Code/MiSTeX-devel/MiSTeX-boards/venv/lib/python3.10/site-packages/litex/soc/software/libc/Makefile']' returned non-zero exit status 2.
Solution:
Add ninja to requirements.txt
'set_property' expects at least one object
Hello, I am stuck by running:
python3 mistex_boards/qmtech_xc7a100t_daughterboard.py Menu
specifically at the part of building the core in Vivado part, here is my vivado.log:
#-----------------------------------------------------------
# Vivado v2023.1 (64-bit)
# SW Build 3865809 on Sun May 7 15:04:56 MDT 2023
# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
# Start of session at: Thu Jun 15 23:34:36 2023
# Process ID: 122601
# Current directory: /home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu
# Command line: vivado -mode batch -source Menu_MiSTeX.tcl
# Log file: /home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/vivado.log
# Journal file: /home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/vivado.jou
# Running On: pc-quarto, OS: Linux, CPU Frequency: 4284.483 MHz, CPU Physical cores: 16, Host memory: 16686 MB
#-----------------------------------------------------------
source Menu_MiSTeX.tcl
# create_project -force -name Menu_MiSTeX -part xc7a100tfgg676-1
create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1332.016 ; gain = 0.023 ; free physical = 1623 ; free virtual = 10076
# set_msg_config -id {Common 17-55} -new_severity {Warning}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/alsa.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/alsa.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/altera_pll_reconfig_core.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/altera_pll_reconfig_top.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/arcade_video.v}
# read_vhdl -vhdl2008 {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ascal.vhd}
# set_property library work [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ascal.vhd}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/audio_out.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ddr_svc.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ddr_svc.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/f2sdram_safe_terminator.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/f2sdram_safe_terminator.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/gamma_corr.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/gamma_corr.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/hps_interface.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/hps_io.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/hps_io.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/hq2x.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/hq2x.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/i2c.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/i2s.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/iir_filter.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ltc2308.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ltc2308.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/math.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/math.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/mcp23009.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/mcp23009.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/mt32pi.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/mt32pi.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/osd.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_audio.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_cfg.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_hdmi.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_hdmi_0002-xilinx7.v}
# read_vhdl -vhdl2008 {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_hdmi_adj.vhd}
# set_property library work [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_hdmi_adj.vhd}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/scandoubler.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/scanlines.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sd_card.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sd_card.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/shadowmask.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/shadowmask.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sigma_delta_dac.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/spdif.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/spi-master.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/spi-slave.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sys_top.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sysmem.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sysmem.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/top_crg.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/vga_out.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/vga_out.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_cleaner.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_cleaner.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_freak.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_freak.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_freezer.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_freezer.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_mixer.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_mixer.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/yc_out.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/yc_out.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/cos.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/cos.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/ddram.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/ddram.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/lfsr.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/pll.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/sdram.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/sdram.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/pll_0002-xilinx7.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_audio_0002-xilinx7.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/build_id.vh}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/menu.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/menu.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/femtorv32_quark.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/Menu_MiSTeX.v}
# read_xdc Menu_MiSTeX.xdc
# set_property PROCESSING_ORDER EARLY [get_files Menu_MiSTeX.xdc]
WARNING: [Vivado 12-818] No files matched '../../../cores/Menu/build_id.vh'
# set_property is_global_include true [get_files "../../../cores/Menu/build_id.vh"]
WARNING: [Common 17-239] ERROR Messages are prohibited to be downgraded. Message 'Common 17-55' is not downgraded.
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
INFO: [Common 17-206] Exiting Vivado at Thu Jun 15 23:34:44 2023...
The whole output from the QMTech xc7a100t board is:
$ python3 mistex_boards/qmtech_xc7a100t_daughterboard.py Menu
******** source directory sys ********
-> cores/Template/sys/alsa.sv
-> cores/Template/sys/altera_pll_reconfig_core.v
-> cores/Template/sys/altera_pll_reconfig_top.v
-> cores/Template/sys/arcade_video.v
-> cores/Template/sys/ascal.vhd
-> cores/Template/sys/audio_out.v
-> cores/Template/sys/ddr_svc.sv
-> cores/Template/sys/f2sdram_safe_terminator.sv
-> cores/Template/sys/gamma_corr.sv
cores/Template/sys/hdmi_config.sv is excluded...
-> cores/Template/sys/hps_interface.v
-> cores/Template/sys/hps_io.sv
-> cores/Template/sys/hq2x.sv
-> cores/Template/sys/i2c.v
-> cores/Template/sys/i2s.v
-> cores/Template/sys/iir_filter.v
-> cores/Template/sys/ltc2308.sv
-> cores/Template/sys/math.sv
-> cores/Template/sys/mcp23009.sv
-> cores/Template/sys/mt32pi.sv
-> cores/Template/sys/osd.v
-> cores/Template/sys/pll_audio.v
cores/Template/sys/pll_audio_0002-xilinx7.v is excluded...
cores/Template/sys/pll_audio_0002.v is excluded...
-> cores/Template/sys/pll_cfg.v
-> cores/Template/sys/pll_hdmi.v
-> cores/Template/sys/pll_hdmi_0002-xilinx7.v
cores/Template/sys/pll_hdmi_0002.v is excluded...
-> cores/Template/sys/pll_hdmi_adj.vhd
-> cores/Template/sys/scandoubler.v
-> cores/Template/sys/scanlines.v
-> cores/Template/sys/sd_card.sv
-> cores/Template/sys/shadowmask.sv
-> cores/Template/sys/sigma_delta_dac.v
-> cores/Template/sys/spdif.v
-> cores/Template/sys/spi-master.v
-> cores/Template/sys/spi-slave.v
cores/Template/sys/sys_top.sdc is excluded...
-> cores/Template/sys/sys_top.v
-> cores/Template/sys/sysmem.sv
-> cores/Template/sys/top_crg.v
-> cores/Template/sys/vga_out.sv
-> cores/Template/sys/video_cleaner.sv
-> cores/Template/sys/video_freak.sv
-> cores/Template/sys/video_freezer.sv
-> cores/Template/sys/video_mixer.sv
-> cores/Template/sys/yc_out.sv
******** source directory rtl ********
-> cores/Menu/rtl/cos.sv
-> cores/Menu/rtl/ddram.sv
-> cores/Menu/rtl/lfsr.v
-> cores/Menu/rtl/pll.v
cores/Menu/rtl/pll_0002-xilinx7.v is excluded...
cores/Menu/rtl/pll_0002.v is excluded...
-> cores/Menu/rtl/sdram.sv
******** source files ********
******** board specific sources ********
-> cores/Menu/rtl/pll_0002-xilinx7.v
-> cores/Template/sys/pll_audio_0002-xilinx7.v
Generating cores/Menu/build_id.vh..
Adding main file cores/Menu/menu.sv
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2023-06-15 23:34:31)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc7a100tfgg676-1.
INFO:SoC:System clock: 125.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU femtorv added.
INFO:SoC:CPU femtorv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU femtorv setting reset address to 0x00000000.
INFO:SoC:CPU femtorv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00008000, Mode: RX, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00008000, Mode: RX, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x01000000, Size: 0x00001000, Mode: RWX, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x01000000, Size: 0x00001000, Mode: RWX, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x08000000, Mode: RWX, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
Compat: SoCCore.add_wb_master is deprecated since 2022-11-03 and will soon no longer work, please update. Switch to SoC.bus.add_master(...)...........thanks :)
INFO:SoCBusHandler:master1 added as Bus Master.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4).
INFO:SoCCSRHandler:analyzer CSR allocated at Location 0.
INFO:SoCCSRHandler:ctrl CSR allocated at Location 1.
INFO:SoCCSRHandler:ddrphy CSR allocated at Location 2.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 3.
INFO:SoCCSRHandler:sdram CSR allocated at Location 4.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:SoCCSRHandler:uart CSR allocated at Location 6.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (4)
rom : Origin: 0x00000000, Size: 0x00008000, Mode: RX, Cached: True Linker: False
sram : Origin: 0x01000000, Size: 0x00001000, Mode: RWX, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x08000000, Mode: RWX, Cached: True Linker: False
csr : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (2)
- cpu_bus0
- master1
Bus Slaves: (4)
- rom
- sram
- main_ram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (7)
- analyzer : 0
- ctrl : 1
- ddrphy : 2
- identifier_mem : 3
- sdram : 4
- timer0 : 5
- uart : 6
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:S7PLL:Config:
divclk_divide : 1
clkout3_freq : 200.00MHz
clkout3_divide: 5
clkout3_phase : 0.00°
clkout4_freq : 50.00MHz
clkout4_divide: 20
clkout4_phase : 0.00°
clkout5_freq : 100.00MHz
clkout5_divide: 10
clkout5_phase : 0.00°
clkout0_freq : 125.00MHz
clkout0_divide: 8
clkout0_phase : 0.00°
clkout1_freq : 500.00MHz
clkout1_divide: 2
clkout1_phase : 0.00°
clkout2_freq : 500.00MHz
clkout2_divide: 2
clkout2_phase : 90.00°
vco : 1000.00MHz
clkfbout_mult : 20
INFO:S7PLL:Config:
divclk_divide : 1
clkout0_freq : 73.81MHz
clkout0_divide: 21
clkout0_phase : 0.00°
vco : 1550.00MHz
clkfbout_mult : 31
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:SoC Hierarchy:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:
BaseSoC
└─── crg (_CRG)
│ └─── pll (S7PLL)
│ │ └─── [FDCE]
│ │ └─── [FDCE]
│ │ └─── [BUFG]
│ │ └─── [FDCE]
│ │ └─── [PLLE2_ADV]
│ │ └─── [BUFG]
│ │ └─── [FDCE]
│ │ └─── [BUFG]
│ │ └─── [FDCE]
│ │ └─── [BUFG]
│ │ └─── [BUFG]
│ │ └─── [FDCE]
│ │ └─── [FDCE]
│ │ └─── [BUFG]
│ │ └─── [FDCE]
│ └─── hdmipll (S7PLL)
│ │ └─── [FDCE]
│ │ └─── [FDCE]
│ │ └─── [PLLE2_ADV]
│ │ └─── [FDCE]
│ │ └─── [FDCE]
│ │ └─── [FDCE]
│ │ └─── [BUFG]
│ │ └─── [FDCE]
│ │ └─── [FDCE]
│ │ └─── [FDCE]
│ └─── idelayctrl (S7IDELAYCTRL)
│ │ └─── [IDELAYCTRL]
└─── bus (SoCBusHandler)
│ └─── _interconnect (InterconnectShared)
│ │ └─── arbiter (Arbiter)
│ │ │ └─── rr (RoundRobin)
│ │ └─── decoder (Decoder)
│ │ └─── timeout (Timeout)
│ │ │ └─── waittimer_0* (WaitTimer)
└─── csr (SoCCSRHandler)
└─── irq (SoCIRQHandler)
└─── ctrl (SoCController)
│ └─── _reset (CSRStorage)
│ └─── _scratch (CSRStorage)
│ └─── _bus_errors (CSRStatus)
└─── cpu (FemtoRV)
│ └─── fsm (FSM)
│ └─── [FemtoRV32]
└─── rom (SRAM)
└─── sram (SRAM)
└─── identifier (Identifier)
└─── uart_phy (RS232PHY)
│ └─── tx (RS232PHYTX)
│ │ └─── rs232clkphaseaccum_0* (RS232ClkPhaseAccum)
│ │ └─── fsm (FSM)
│ └─── rx (RS232PHYRX)
│ │ └─── rs232clkphaseaccum_0* (RS232ClkPhaseAccum)
│ │ └─── fsm (FSM)
└─── uart (UART)
│ └─── ev (EventManager)
│ │ └─── eventsourceprocess_0* (EventSourceProcess)
│ │ └─── eventsourceprocess_1* (EventSourceProcess)
│ └─── tx_fifo (SyncFIFO)
│ │ └─── fifo (SyncFIFOBuffered)
│ │ │ └─── fifo (SyncFIFO)
│ └─── rx_fifo (SyncFIFO)
│ │ └─── fifo (SyncFIFOBuffered)
│ │ │ └─── fifo (SyncFIFO)
└─── timer0 (Timer)
│ └─── ev (EventManager)
│ │ └─── eventsourceprocess_0* (EventSourceProcess)
└─── ddrphy (A7DDRPHY)
│ └─── tappeddelayline_0* (TappedDelayLine)
│ └─── dqspattern_0* (DQSPattern)
│ └─── bitslip_0* (BitSlip)
│ └─── bitslip_1* (BitSlip)
│ └─── tappeddelayline_1* (TappedDelayLine)
│ └─── bitslip_2* (BitSlip)
│ └─── bitslip_3* (BitSlip)
│ └─── bitslip_4* (BitSlip)
│ └─── bitslip_5* (BitSlip)
│ └─── bitslip_6* (BitSlip)
│ └─── bitslip_7* (BitSlip)
│ └─── bitslip_8* (BitSlip)
│ └─── bitslip_9* (BitSlip)
│ └─── bitslip_10* (BitSlip)
│ └─── bitslip_11* (BitSlip)
│ └─── bitslip_12* (BitSlip)
│ └─── bitslip_13* (BitSlip)
│ └─── bitslip_14* (BitSlip)
│ └─── bitslip_15* (BitSlip)
│ └─── bitslip_16* (BitSlip)
│ └─── bitslip_17* (BitSlip)
│ └─── tappeddelayline_2* (TappedDelayLine)
│ └─── tappeddelayline_3* (TappedDelayLine)
│ └─── [OSERDESE2]
│ └─── [IDELAYE2]
│ └─── [IOBUF]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [ISERDESE2]
│ └─── [IDELAYE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [IOBUF]
│ └─── [ISERDESE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [IDELAYE2]
│ └─── [ISERDESE2]
│ └─── [OBUFDS]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [ISERDESE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [IDELAYE2]
│ └─── [OSERDESE2]
│ └─── [ISERDESE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [IOBUF]
│ └─── [IOBUF]
│ └─── [IDELAYE2]
│ └─── [IOBUF]
│ └─── [OSERDESE2]
│ └─── [ISERDESE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [IOBUF]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [IDELAYE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [IOBUFDS]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
│ └─── [IDELAYE2]
│ └─── [IOBUF]
│ └─── [OSERDESE2]
│ └─── [ISERDESE2]
│ └─── [IOBUF]
│ └─── [OSERDESE2]
│ └─── [ISERDESE2]
│ └─── [IDELAYE2]
│ └─── [OSERDESE2]
│ └─── [OSERDESE2]
└─── sdram (LiteDRAMCore)
│ └─── dfii (DFIInjector)
│ │ └─── pi0 (PhaseInjector)
│ │ └─── pi1 (PhaseInjector)
│ │ └─── pi2 (PhaseInjector)
│ │ └─── pi3 (PhaseInjector)
│ └─── controller (LiteDRAMController)
│ │ └─── refresher (Refresher)
│ │ │ └─── timer (RefreshTimer)
│ │ │ └─── postponer (RefreshPostponer)
│ │ │ └─── sequencer (RefreshSequencer)
│ │ │ │ └─── refreshexecuter_0* (RefreshExecuter)
│ │ │ └─── zqcs_timer (RefreshTimer)
│ │ │ └─── zqs_executer (ZQCSExecuter)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_0* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_1* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_2* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_3* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_4* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_5* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_6* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── bankmachine_7* (BankMachine)
│ │ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ │ └─── buffer_0* (Buffer)
│ │ │ │ └─── pipe_valid (PipeValid)
│ │ │ │ └─── pipeline (Pipeline)
│ │ │ └─── twtpcon (tXXDController)
│ │ │ └─── trccon (tXXDController)
│ │ │ └─── trascon (tXXDController)
│ │ │ └─── fsm (FSM)
│ │ └─── multiplexer (Multiplexer)
│ │ │ └─── choose_cmd (_CommandChooser)
│ │ │ │ └─── roundrobin_0* (RoundRobin)
│ │ │ └─── choose_req (_CommandChooser)
│ │ │ │ └─── roundrobin_0* (RoundRobin)
│ │ │ └─── _steerer_0* (_Steerer)
│ │ │ └─── trrdcon (tXXDController)
│ │ │ └─── tfawcon (tFAWController)
│ │ │ └─── tccdcon (tXXDController)
│ │ │ └─── twtrcon (tXXDController)
│ │ │ └─── fsm (FSM)
│ └─── crossbar (LiteDRAMCrossbar)
│ │ └─── litedramnativeportcdc_0* (LiteDRAMNativePortCDC)
│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing)
│ │ │ │ └─── asyncfifo_0* (AsyncFIFO)
│ │ │ │ │ └─── fifo (AsyncFIFO)
│ │ │ │ │ │ └─── graycounter_0* (GrayCounter)
│ │ │ │ │ │ └─── graycounter_1* (GrayCounter)
│ │ │ └─── pipeline_0* (Pipeline)
│ │ │ └─── clockdomaincrossing_1* (ClockDomainCrossing)
│ │ │ │ └─── asyncfifo_0* (AsyncFIFO)
│ │ │ │ │ └─── fifo (AsyncFIFO)
│ │ │ │ │ │ └─── graycounter_0* (GrayCounter)
│ │ │ │ │ │ └─── graycounter_1* (GrayCounter)
│ │ │ └─── pipeline_1* (Pipeline)
│ │ │ └─── clockdomaincrossing_2* (ClockDomainCrossing)
│ │ │ │ └─── asyncfifo_0* (AsyncFIFO)
│ │ │ │ │ └─── fifo (AsyncFIFO)
│ │ │ │ │ │ └─── graycounter_0* (GrayCounter)
│ │ │ │ │ │ └─── graycounter_1* (GrayCounter)
│ │ │ └─── pipeline_2* (Pipeline)
│ │ └─── roundrobin_0* (RoundRobin)
│ │ └─── roundrobin_1* (RoundRobin)
│ │ └─── roundrobin_2* (RoundRobin)
│ │ └─── roundrobin_3* (RoundRobin)
│ │ └─── roundrobin_4* (RoundRobin)
│ │ └─── roundrobin_5* (RoundRobin)
│ │ └─── roundrobin_6* (RoundRobin)
│ │ └─── roundrobin_7* (RoundRobin)
└─── converter_0* (Converter)
│ └─── upconverter_0* (UpConverter)
└─── wishbone_bridge (LiteDRAMWishbone2Native)
│ └─── fsm (FSM)
└─── gamecore (Gamecore)
│ └─── scaler_avalon_port (LiteDRAMAvalonMM2Native)
│ │ └─── fsm (FSM)
│ │ └─── cmd_fifo (SyncFIFO)
│ │ │ └─── fifo (SyncFIFO)
│ │ └─── wdata_fifo (SyncFIFO)
│ │ │ └─── fifo (SyncFIFO)
│ └─── emu_avalon_port (LiteDRAMAvalonMM2Native)
│ │ └─── fsm (FSM)
│ │ └─── cmd_fifo (SyncFIFO)
│ │ │ └─── fifo (SyncFIFO)
│ │ └─── wdata_fifo (SyncFIFO)
│ │ │ └─── fifo (SyncFIFO)
│ └─── avalon_start_delay (WaitTimer)
│ └─── [sys_top]
└─── spibone (SPIBone)
│ └─── fsm_0* (FSM)
└─── analyzer (LiteScopeAnalyzer)
│ └─── mux (_Mux)
│ └─── trigger (_Trigger)
│ │ └─── asyncfifo_0* (AsyncFIFO)
│ │ │ └─── fifo (AsyncFIFO)
│ │ │ │ └─── graycounter_0* (GrayCounter)
│ │ │ │ └─── graycounter_1* (GrayCounter)
│ │ └─── waittimer_0* (WaitTimer)
│ └─── subsampler (_SubSampler)
│ └─── storage (_Storage)
│ │ └─── syncfifo_0* (SyncFIFO)
│ │ │ └─── fifo (SyncFIFOBuffered)
│ │ │ │ └─── fifo (SyncFIFO)
│ │ └─── asyncfifo_0* (AsyncFIFO)
│ │ │ └─── fifo (AsyncFIFO)
│ │ │ │ └─── graycounter_0* (GrayCounter)
│ │ │ │ └─── graycounter_1* (GrayCounter)
│ │ └─── waittimer_0* (WaitTimer)
│ │ └─── fsm_0* (FSM)
│ │ └─── converter_0* (Converter)
│ │ │ └─── _downconverter_0* (_DownConverter)
│ └─── pipeline (Pipeline)
└─── csr_bridge (Wishbone2CSR)
│ └─── fsm_0* (FSM)
└─── csr_bankarray (CSRBankArray)
│ └─── csrbank_0* (CSRBank)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstorage_1* (CSRStorage)
│ │ └─── csrstatus_0* (CSRStatus)
│ │ └─── csrstorage_2* (CSRStorage)
│ │ └─── csrstorage_3* (CSRStorage)
│ │ └─── csrstatus_1* (CSRStatus)
│ │ └─── csrstorage_4* (CSRStorage)
│ │ └─── csrstorage_5* (CSRStorage)
│ │ └─── csrstatus_2* (CSRStatus)
│ │ └─── csrstorage_6* (CSRStorage)
│ │ └─── csrstorage_7* (CSRStorage)
│ │ └─── csrstatus_3* (CSRStatus)
│ │ └─── csrstatus_4* (CSRStatus)
│ └─── csrbank_1* (CSRBank)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstorage_1* (CSRStorage)
│ │ └─── csrstatus_0* (CSRStatus)
│ └─── csrbank_2* (CSRBank)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstorage_1* (CSRStorage)
│ │ └─── csrstorage_2* (CSRStorage)
│ │ └─── csrstorage_3* (CSRStorage)
│ │ └─── csrstorage_4* (CSRStorage)
│ │ └─── csrstorage_5* (CSRStorage)
│ └─── sram_0* (SRAM)
│ └─── csrbank_3* (CSRBank)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstorage_1* (CSRStorage)
│ │ └─── csrstorage_2* (CSRStorage)
│ │ └─── csrstorage_3* (CSRStorage)
│ │ └─── csrstorage_4* (CSRStorage)
│ │ └─── csrstatus_0* (CSRStatus)
│ │ └─── csrstorage_5* (CSRStorage)
│ │ └─── csrstorage_6* (CSRStorage)
│ │ └─── csrstorage_7* (CSRStorage)
│ │ └─── csrstorage_8* (CSRStorage)
│ │ └─── csrstatus_1* (CSRStatus)
│ │ └─── csrstorage_9* (CSRStorage)
│ │ └─── csrstorage_10* (CSRStorage)
│ │ └─── csrstorage_11* (CSRStorage)
│ │ └─── csrstorage_12* (CSRStorage)
│ │ └─── csrstatus_2* (CSRStatus)
│ │ └─── csrstorage_13* (CSRStorage)
│ │ └─── csrstorage_14* (CSRStorage)
│ │ └─── csrstorage_15* (CSRStorage)
│ │ └─── csrstorage_16* (CSRStorage)
│ │ └─── csrstatus_3* (CSRStatus)
│ └─── csrbank_4* (CSRBank)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstorage_1* (CSRStorage)
│ │ └─── csrstorage_2* (CSRStorage)
│ │ └─── csrstorage_3* (CSRStorage)
│ │ └─── csrstatus_0* (CSRStatus)
│ │ └─── csrstatus_1* (CSRStatus)
│ │ └─── csrstatus_2* (CSRStatus)
│ │ └─── csrstorage_4* (CSRStorage)
│ └─── csrbank_5* (CSRBank)
│ │ └─── csrstatus_0* (CSRStatus)
│ │ └─── csrstatus_1* (CSRStatus)
│ │ └─── csrstatus_2* (CSRStatus)
│ │ └─── csrstatus_3* (CSRStatus)
│ │ └─── csrstorage_0* (CSRStorage)
│ │ └─── csrstatus_4* (CSRStatus)
│ │ └─── csrstatus_5* (CSRStatus)
└─── csr_interconnect (InterconnectShared)
* : Generated name.
[]: BlackBox.
INFO:SoC:--------------------------------------------------------------------------------
make: Entrando no diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/libc'
make: Nada a ser feito para 'all'.
make: Saindo do diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/libc'
make: Entrando no diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/libcompiler_rt'
make: Nada a ser feito para 'all'.
make: Saindo do diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/libcompiler_rt'
make: Entrando no diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/libbase'
CC console.o
CC system.o
CC memtest.o
CC uart.o
CC spiflash.o
CC i2c.o
CC isr.o
AR libbase.a
make: Saindo do diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/libbase'
make: Entrando no diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/libfatfs'
make: Nada a ser feito para 'all'.
make: Saindo do diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/libfatfs'
make: Entrando no diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/liblitespi'
CC spiflash.o
AR liblitespi.a
make: Saindo do diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/liblitespi'
make: Entrando no diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/liblitedram'
CC sdram.o
/home/chandler/.local/lib/python3.11/site-packages/litex/soc/software/liblitedram/sdram.c:241:5: warning: no previous prototype for 'swap_bit' [-Wmissing-prototypes]
241 | int swap_bit(int num, int a, int b) {
| ^~~~~~~~
CC bist.o
CC sdram_dbg.o
CC sdram_spd.o
CC utils.o
CC accessors.o
AR liblitedram.a
make: Saindo do diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/liblitedram'
make: Entrando no diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/libliteeth'
CC udp.o
CC mdio.o
AR libliteeth.a
make: Saindo do diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/libliteeth'
make: Entrando no diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/liblitesdcard'
CC sdcard.o
CC spisdcard.o
AR liblitesdcard.a
make: Saindo do diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/liblitesdcard'
make: Entrando no diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/liblitesata'
CC sata.o
AR liblitesata.a
make: Saindo do diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/liblitesata'
make: Entrando no diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/bios'
CC boot.o
CC cmd_bios.o
CC cmd_mem.o
CC cmd_boot.o
CC cmd_i2c.o
CC cmd_spiflash.o
CC cmd_litedram.o
CC cmd_liteeth.o
CC cmd_litesdcard.o
CC cmd_litesata.o
CC sim_debug.o
CC main.o
CC bios.elf
/usr/bin/../lib/gcc/riscv64-unknown-elf/12.2.0/../../../../riscv64-unknown-elf/bin/ld: warning: bios.elf has a LOAD segment with RWX permissions
chmod -x bios.elf
OBJCOPY bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.crcfbigen bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/bios/../include/generated/regions.ld riscv64-unknown-elf
ROM usage: 27.73KiB (86.67%)
RAM usage: 1.35KiB (33.79%)
make: Saindo do diretório '/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/software/bios'
INFO:SoC:Initializing ROM rom with contents (Size: 0x6f00).
INFO:SoC:Auto-Resizing ROM rom from 0x8000 to 0x6f00.
****** Vivado v2023.1 (64-bit)
**** SW Build 3865809 on Sun May 7 15:04:56 MDT 2023
**** IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
**** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source Menu_MiSTeX.tcl
# create_project -force -name Menu_MiSTeX -part xc7a100tfgg676-1
create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1332.016 ; gain = 0.023 ; free physical = 1623 ; free virtual = 10076
# set_msg_config -id {Common 17-55} -new_severity {Warning}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/alsa.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/alsa.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/altera_pll_reconfig_core.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/altera_pll_reconfig_top.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/arcade_video.v}
# read_vhdl -vhdl2008 {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ascal.vhd}
# set_property library work [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ascal.vhd}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/audio_out.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ddr_svc.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ddr_svc.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/f2sdram_safe_terminator.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/f2sdram_safe_terminator.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/gamma_corr.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/gamma_corr.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/hps_interface.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/hps_io.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/hps_io.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/hq2x.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/hq2x.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/i2c.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/i2s.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/iir_filter.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ltc2308.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/ltc2308.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/math.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/math.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/mcp23009.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/mcp23009.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/mt32pi.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/mt32pi.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/osd.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_audio.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_cfg.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_hdmi.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_hdmi_0002-xilinx7.v}
# read_vhdl -vhdl2008 {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_hdmi_adj.vhd}
# set_property library work [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_hdmi_adj.vhd}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/scandoubler.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/scanlines.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sd_card.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sd_card.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/shadowmask.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/shadowmask.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sigma_delta_dac.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/spdif.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/spi-master.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/spi-slave.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sys_top.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sysmem.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/sysmem.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/top_crg.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/vga_out.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/vga_out.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_cleaner.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_cleaner.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_freak.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_freak.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_freezer.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_freezer.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_mixer.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/video_mixer.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/yc_out.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/yc_out.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/cos.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/cos.sv}]
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/ddram.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/ddram.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/lfsr.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/pll.v}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/sdram.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/sdram.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/rtl/pll_0002-xilinx7.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Template/sys/pll_audio_0002-xilinx7.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/build_id.vh}
# read_verilog -v {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/menu.sv}
# set_property file_type SystemVerilog [get_files {/home/chandler/Documentos/MiSTeX-boards/cores/Menu/menu.sv}]
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/femtorv32_quark.v}
# read_verilog {/home/chandler/Documentos/MiSTeX-boards/build/mistex_boards/qmtech_xc7a100t_daughterboard/Menu/Menu_MiSTeX.v}
# read_xdc Menu_MiSTeX.xdc
# set_property PROCESSING_ORDER EARLY [get_files Menu_MiSTeX.xdc]
WARNING: [Vivado 12-818] No files matched '../../../cores/Menu/build_id.vh'
# set_property is_global_include true [get_files "../../../cores/Menu/build_id.vh"]
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Common 17-239] ERROR Messages are prohibited to be downgraded. Message 'Common 17-55' is not downgraded.
INFO: [Common 17-206] Exiting Vivado at Thu Jun 15 23:34:44 2023...
Traceback (most recent call last):
File "/home/chandler/Documentos/MiSTeX-boards/mistex_boards/qmtech_xc7a100t_daughterboard.py", line 430, in <module>
handle_main(main)
File "/home/chandler/Documentos/MiSTeX-boards/mistex_boards/util.py", line 81, in handle_main
main(core=sys.argv[1])
File "/home/chandler/Documentos/MiSTeX-boards/mistex_boards/qmtech_xc7a100t_daughterboard.py", line 427, in main
builder.build(build_name = get_build_name(core))
File "/home/chandler/.local/lib/python3.11/site-packages/litex/soc/integration/builder.py", line 367, in build
vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/chandler/.local/lib/python3.11/site-packages/litex/soc/integration/soc.py", line 1322, in build
return self.platform.build(self, *args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/chandler/.local/lib/python3.11/site-packages/litex/build/xilinx/platform.py", line 85, in build
return self.toolchain.build(self, *args, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/chandler/.local/lib/python3.11/site-packages/litex/build/xilinx/vivado.py", line 140, in build
return GenericToolchain.build(self, platform, fragment, **kwargs)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/home/chandler/.local/lib/python3.11/site-packages/litex/build/generic_toolchain.py", line 118, in build
self.run_script(script)
File "/home/chandler/.local/lib/python3.11/site-packages/litex/build/xilinx/vivado.py", line 392, in run_script
raise OSError("Error occured during Vivado's script execution.")
OSError: Error occured during Vivado's script execution.
Can someone tell me why Vivado complained about this error:
ERROR: [Common 17-55] 'set_property' expects at least one object.
Thanks in advance!!
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