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Hi! My name is Khadija.

Computer Systems Engineering | Hardware Design Engineer

💻 Languages and Tools:

Visual Studio Code



🚀Other Stuff...


👩‍💻 I'm currently working on designing and verifying the RISCV based Processors and Soc, involved in projects related to my work for further enhancement and learning purposes.

🧠 My main motive for this year is to expand my literacy and willingly learn and contribute more to open source projects.

👯‍♀️ I'm looking to collaborate on more Open Source Projects which include development of RISCV and implementation.

🤔 I'm looking for help with UVM. Currently learning new skills according to development era which includes world of Metaverse and AI.

📫 Reach me via: [email protected]

😄 Fun facts: Eagerly willing to learn new things every minute.


⚡️ Github Stats Khadija's github stats
⚡️ Languages Used

Khadija's Projects

ibex icon ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

openpiton icon openpiton

MARCore Multi core System On Chip for SMP Linux based on Openpiton

oppia icon oppia

A free, online learning platform to make quality education accessible for all.

rv32i icon rv32i

RISC-V (RV32-I) is single cycle processor in system verilog

serv icon serv

SERV - The SErial RISC-V CPU

sootty icon sootty

A command-line tool for displaying vcd waveforms.

verible icon verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

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