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Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

Home Page: https://chipsalliance.github.io/verible/

License: Apache License 2.0

C++ 88.86% Shell 2.58% Lex 0.77% Yacc 3.73% Starlark 3.35% Awk 0.05% Dockerfile 0.01% Python 0.59% Nix 0.01% Makefile 0.01% TypeScript 0.02% JavaScript 0.02%

verible's Introduction

Hi! My name is Khadija.

Computer Systems Engineering | Hardware Design Engineer

💻 Languages and Tools:

Visual Studio Code



🚀Other Stuff...


👩‍💻 I'm currently working on designing and verifying the RISCV based Processors and Soc, involved in projects related to my work for further enhancement and learning purposes.

🧠 My main motive for this year is to expand my literacy and willingly learn and contribute more to open source projects.

👯‍♀️ I'm looking to collaborate on more Open Source Projects which include development of RISCV and implementation.

🤔 I'm looking for help with UVM. Currently learning new skills according to development era which includes world of Metaverse and AI.

📫 Reach me via: [email protected]

😄 Fun facts: Eagerly willing to learn new things every minute.


⚡️ Github Stats Khadija's github stats
⚡️ Languages Used

verible's People

Contributors

admud avatar ahmedkrmn avatar alex-mann avatar cclauss avatar ciprian167 avatar corco avatar fangism avatar hzeller avatar imphil avatar ivan444 avatar johanvdhaegen avatar jonathankimmitt avatar jonmayergoogle avatar karimtera avatar kaustubhgc-g avatar mglb avatar michael-etzkorn avatar minatoma avatar mithro avatar newam avatar omarahmed1111 avatar preusser avatar sethvargo avatar snsokolov avatar tgorochowik avatar theswit avatar umarcor avatar wsipak avatar wtatarski avatar zegervdv avatar

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