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SERV - The SErial RISC-V CPU

License: ISC License

Verilog 79.89% C 7.30% Python 0.91% SystemVerilog 1.92% C++ 4.96% Makefile 0.19% Assembly 1.82% Tcl 2.14% CMake 0.58% Mathematica 0.29%

serv's Introduction

Hi! My name is Khadija.

Computer Systems Engineering | Hardware Design Engineer

💻 Languages and Tools:

Visual Studio Code



🚀Other Stuff...


👩‍💻 I'm currently working on designing and verifying the RISCV based Processors and Soc, involved in projects related to my work for further enhancement and learning purposes.

🧠 My main motive for this year is to expand my literacy and willingly learn and contribute more to open source projects.

👯‍♀️ I'm looking to collaborate on more Open Source Projects which include development of RISCV and implementation.

🤔 I'm looking for help with UVM. Currently learning new skills according to development era which includes world of Metaverse and AI.

📫 Reach me via: [email protected]

😄 Fun facts: Eagerly willing to learn new things every minute.


⚡️ Github Stats Khadija's github stats
⚡️ Languages Used

serv's People

Contributors

alalves avatar brunoflores avatar ddribin avatar dh73 avatar drom avatar ekiwi avatar emeb avatar gitter-badger avatar hakan-demirli avatar imuguruza avatar jansenarruda avatar kholia avatar klasnordmark avatar martoni avatar mtnrbq avatar nalzok avatar olofk avatar seguraeng avatar smunaut avatar somhi avatar soumilheble avatar tomverbeure avatar trabucayre avatar wallento avatar zarubaf avatar zeeshanrafique23 avatar

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