Comments (8)
Yes, the use of a0
for environment calls is to match what venus does. However, i would be very open to aligning with the gnu toolchain or some other standard, and i think there is great value in aligning the three applications (Venus, Ripes and RARS) given that each application is a valuable teaching tool on its own, whilst still complementing each other.
I have not implementing a testing interface for Ripes - embarrassingly enough, most testing of Ripes is manual testing. The reason is, that there exists a high degree of coupling between the UI, assembler and simulator, which makes headless testing quite awkward.
There is currently no active development on Ripes, given that i am focusing most of my time on VSRTL. Once in a stable state, VSRTL is intended to be used in a revised version of Ripes, which should make a lot of things - including testing - much simpler.
I have considered creating a temporary testing interface for Ripes which would be able to execute unit tests, albeit slowly. This has however not yet been done - mostly because of my focus on VSRTL. But given your test suite, i'll see if i can get something implemented soon.
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I manually tested a few of RARs tests and it seems like aside from system calls, they're fairly compatible. A few missing directives like .global
and .space
stopped a copy paste compilation. I would be willing to add small compatibility features like those if it would be merged in.
Once in a stable state, VSRTL is intended to be used in a revised version of Ripes, which should make a lot of things - including testing - much simpler
How much is it intended to change? Should I hold off on adding directives and such until the revised version is completed?
Also, I found a bug in mulhu
. I believe it will only ever output 0 because the inputs are multiplied as uint32_t
instead of uint64_t
.
Here is a snippet of a failing test from RARS's test:
.text
main:
test_7:
li x1, 0x80000000
li x2, 0xffff8000
mulhu x30, x1, x2 # ALU ouputs 0
li x29, 0x7fffc000
bne x30, x29, fail
pass:
li a0, 42
li a7, 93
ecall
fail:
li a0, 0
li a7, 93
ecall
If you want I can manually test some more instructions that might be problematic.
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I manually tested a few of RARs tests and it seems like aside from system calls, they're fairly compatible. A few missing directives like
.global
and.space
stopped a copy paste compilation. I would be willing to add small compatibility features like those if it would be merged in.
This would purely require changes in the assembler, and are welcome changes.
Once in a stable state, VSRTL is intended to be used in a revised version of Ripes, which should make a lot of things - including testing - much simpler
How much is it intended to change? Should I hold off on adding directives and such until the revised version is completed?
These changes will be on a simulator level and will not be connected to anything assembler related, so as above.
Also, I found a bug in
mulhu
. I believe it will only ever output 0 because the inputs are multiplied asuint32_t
instead ofuint64_t
.
Thank you for finding the issue! I'll take a look on the failing instruction asap.
If you want I can manually test some more instructions that might be problematic.
If you have the time, that would be much appreciated. But to not waste anyones time, having just some form of automatic testing support in Ripes should be a priority.
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a6da9b9 introduces rudimentary unit-testing abilities but is still a step up from manual testing. Feel free to add unit tests by adding files in https://github.com/mortbopet/Ripes/tree/master/test and in the https://github.com/mortbopet/Ripes/blob/master/test/tests.qrc file
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@TheThirdOne Are you still in active development of RARS? I would very much like to get in touch with you regarding future simulators and RISC-V tools.
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@mortbopet, I'm not sure I'd call it "active development", but I generally spend a few hours a week working on new features (currently loading elf files and a better logging system).
I would be happy to talk with you about RISC-V simulators and tools.
from ripes.
@mortbopet, I'm not sure I'd call it "active development", but I generally spend a few hours a week working on new features (currently loading elf files and a better logging system).
I would be happy to talk with you about RISC-V simulators and tools.
Sounds great! I'd like to continue over e-mail, however i generally avoid sharing it on public forums (GitHub really needs a DM feature!). If you have linkedin, you can catch me here.
from ripes.
I have sent an email off to your live dot dk email.
from ripes.
Related Issues (20)
- Open ecall does not support read only mode HOT 1
- Adding a new Verilator processor model HOT 3
- Ripes crashes when hovering over the cache statistics chart HOT 1
- Ripes crashes when using 'Open' Syscall HOT 2
- Error reporting when running on centos7 HOT 2
- Missing virtual destructors in abstract classes
- Discussion on Github Actions HOT 1
- Add Cache Replacement Policy HOT 1
- Setting a register as the first instruction sometimes causes a runtime error in the single-cycle processors
- Using CLI without UI
- Use `magic_enum` to replace various enum<-> name maps and better-enums HOT 1
- M-extension issue (multiplication exceeds 64-bits)
- Division by zero crash in assembler constant expressions
- Adding options for branch strategies and branch delay HOT 1
- "Clock the circuit with the selected frequency" (F6) never stops HOT 5
- How to handle System Input in CLI? HOT 3
- Assembly source code execution highlight only works with default .text start address HOT 2
- Input Type always set to `Assembly` on startup
- Adding an option to change the direction of memory address growth
- .gitignore does not match files generated at configuration/compile time (?)
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