muneeb-mbytes/apb_avip

ABP Accelerated VIP

apb_avip's Issues

Unnecessary wait state detected

pready high is not detected at the access phase of the first transfer. So, a wait state is detected.

Slave signals are multiply driven issue

When no of slaves is greater than 1 then the slave signals i.e., pready, prdata, pslverr are multiply driven to the interface.
The issue is different based on simulators.

1. Questa-sim :
   a. Resulted in warnings when slave signals i.e., pready, prdata, pslverr are declared as logic type in the interface.
   b. If the same signals are declared as wire, then it is entering into the infinite loop.
2. Cadence :
   a. Resulted in compilation errors when slave signals i.e., pready, prdata, pslverr are declared as logic type in the interface.
   b. If the same signals are declared as wire, then it is completely working fine.

Address should not be changed for write read test case

The address used for read transfer should be same as write transfer to verify the continuous write_read transfer.
A variable named cont_write_read is added in master_tx class. That address is stored in master driver proxy when cont_write_read is high and use the same address for read transfer so that read happens from the same address where the master has written.