no2fpga/no2bootloader

USB DFU bootloader gateware / firmware for FPGAs

no2bootloader's Issues

ice40-stub has slightly broken instructions because prerequisites are both depreciated

I had luck with riscv-none-elf though, which replaced it. Work-around(s) follows:

• Used XPM to install https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack (following current instructions there), into a fake project at /opt/xPacks/, I.E.

cd /opt
mkdir xPacks
cd !$
xpm init
xpm install @xpack-dev-tools/riscv-none-elf-gcc@latest
cd

Then put

export PATH="/opt/xPacks/xpacks/.bin:$PATH" # for riscv-none-elf-*

on the end of my .bashrc

• also: YosysHQ/fpga-toolchain is depreciated for YosysHQ/oss-cad-suite-build and/or YoWASP if you really want static binaries (which are very portable). I went with oss-cad-suite-build nightly release tar xf'd into /opt, and also added (again, to .bashrc):

export PATH="/opt/oss-cad-suite/bin:$PATH"

Finally, I could build successfully with:

cd
. .bashrc
cd no2bootloader/gateware/ice40-stub
CROSS=riscv-none-elf- make bootloader

Hope this helps

Porting to Ulx3s and Ulx4m Devices

I am attempting to port this bootloader to the Ulx3s Ecp5 device and then to the new Ulx4m device, which has more need of a dfu bootloader.

I believe you had some discussion with Goran Mahovlic of Radiona on this. He is current getting things working on a prototype Ulx4m device.

@emard, the designer of the Ulx3s device, and I, have looked at porting your had2019-playground version to the Ulx3s, but are currently not making much progress.

So i wanted your advice on the best approach.

The main problems with the had2019 version are the different clock speed and the need for a different pll, and the use of the PSRAM.

I don't know how much the PSRAM is used. I saw that this version uses the SPRAM on the up5k.

On the Ulx3s we could either use SDRAM or BRAM depending on how much is needed.

The Ulx3s has a usb connector (us2) that is connected to the fpga. I have used that for both usb host and usb device with SaxonSoc.

I am not sure if I am best starting with this version of the had2019 version.

Am I right that the had2019 device has an 8Mhz clock, so I will need to change the pll for the 25MHz clock of the Ulx3s. The pll is hand-coded in sysmgr.v and I am not sure what parameters it needs. There are 24MHz, 48Mhz and 96MHz output clocks. I am not sure if any of them have phase shifts.

Cannot make the bootloader for the Icebreaker bitsy :(

turbo@core:~/fpga/bootloader/no2bootloader/gateware/ice40-stub$ make BOARD=bitsy-v1 bootloader
Makefile:33: ../build/project-rules.mk: No such file or directory
make: *** No rule to make target '../build/project-rules.mk'. Stop.
Please send help .-.
I think it has to do with the riscv toolchain but i don't know much about this stuff.

Porting to ICE5LP4K

Is it possible to port bootloader to ICE5LP4K FPGA, main problem is that this chip does not have SPRAM at all, then question is will the RISC-V run on BRAM, will it fit?

Does the clock matter and where can I change the clock freq of the bootloader?

Is there a way to change the clock freq of the bootloader for the icebreaker bitsy?
The original design has a 12Mhz Clock built in, my custom design uses a 40Mhz Clock.
Does this influence the USB bootloader in any way?
Because when i plug it in my pc the power and cdone light goes on but when i hold the button and plug it in there isn't the usb detection sound and the device isn't found in the device manager :(
Hope u can help ._.