Comments (8)
Hi,
You have to move cv32e40p directory somewhere else and use following option when launching make command:
CV_CORE_PATH=<your path>/cv32e40p
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Hi @Attaullah786, did @pascalgouedo answer your question? If so, please close this Issue. If you do not comment within one week, this Issue will be closed.
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Thanks for your answer. When i run the hello world test there is no information about CPI for the test cases. Kindly give me insight about the test cases that gave clock cycles. Thanks
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Hi @Attaullah786'
there is no information about CPI for the test cases
What do you mean by "CPI"?
Kindly give me insight about the test cases that gave clock cycles.
We have no testcases that track clock cycles and there is no function in the testbench that does this. We do not have any verification requirements to measure clock cycles, so this was not added. Why do you need it?
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Even if clock cycles are not useful for verification purpose, we do measure them in the benchmarks.
You can find a simple example of that in matmul_32b_int one.
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I implemented a dynamic w but branch predictor in cv32e40p core. Now I have to analyze whether the branch predictor reduced the execution time for some branch instructions or not. So I need that execution time. Is there any process in the core already to find it?
from cv32e40p.
The CV32E40P implements the mcycle and minstret CSRs. Your test-program could query these.
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I implemented a dynamic w but branch predictor in cv32e40p core. Now I have to analyze whether the branch predictor reduced the execution time for some branch instructions or not. So I need that execution time. Is there any process in the core already to find it?
Already answered above with matmul_32b_int example.
To characterize your branch predictor, I advise you to use Embench Iot 0.5 that you can launch on uvm test-bench.
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Related Issues (20)
- Help needed: Integration of cvFPU with cv32e40p and adding a custom instruction HOT 5
- HW Loop Constraints question HOT 5
- Error in Analysis and Synthesis in Quartus HOT 21
- Missing files HOT 3
- Seeking Information on RTL Access HOT 8
- Incorporating FPU HOT 2
- Suggested update to the FPGA Synthesis sub-section of the User Manual HOT 1
- cv32e40p_obi_interface: When TRANS_STABLE=0, unstable transaction can still pass through to obi interface. HOT 4
- cv32e40p_prefetch_buffer: Is it ok to assert hwlp_jump_i when there are no outstanding instr_ requests (ie cnt_q == 0)? HOT 4
- How can I build this core? HOT 2
- cv32e40p implementation on Arty a7 100T FPGA HOT 2
- Missing case default HOT 1
- Impossible to cover case default HOT 1
- FPU power consumption HOT 1
- Clarification on cv.clipr signedness HOT 2
- HWLoop count not updated when last instruction is a CSR access with pipeline flush HOT 1
- Ensure Makefiles support both SNPS VCS and Siemens Questa for the above HOT 1
- Code coverage report HOT 4
- Floating Point Unit (FPU) not working HOT 1
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