Comments (2)
I am working on it since last week.
Same pb than 1a58c7b#commitcomment-138230716
I have an RTL update (masking MSB directly in HW) for that to definitively resolve the pb for everyone.
Need to fully verify it before changing User Manual clipr/clipur description and pushing it.
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Corrected with PR #971
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Related Issues (20)
- Branch predictor in cv32e40p core will take more time. HOT 8
- cv32e40p_prefetch_buffer: Is it ok to assert hwlp_jump_i when there are no outstanding instr_ requests (ie cnt_q == 0)? HOT 4
- How can I build this core? HOT 2
- cv32e40p implementation on Arty a7 100T FPGA HOT 2
- Missing case default HOT 1
- Impossible to cover case default HOT 1
- FPU power consumption HOT 1
- HWLoop count not updated when last instruction is a CSR access with pipeline flush HOT 1
- Ensure Makefiles support both SNPS VCS and Siemens Questa for the above HOT 1
- Code coverage report HOT 4
- Floating Point Unit (FPU) not working HOT 1
- Debug: Which version of OpenOCD HOT 3
- Combinational loops in synthesis (cv32e40px) when adding co-processor through CV-X-IF HOT 9
- CVFPU RTL updates for implementation tools HOT 2
- Missing area metrics for ASIC synthesis HOT 1
- RTL Code Coverage Hole in cv32e40p_controller module line 399
- RTL Code Coverage Hole in cv32e40p_controller module line 640
- RTL Code Coverage Hole in cv32e40p_controller module lines 632 and 642
- RTL Code Coverage Hole in cv32e40p_controller module line 675
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