Comments (2)
youzi27
commented on June 18, 2024
The vulnerability of the rounding mode mentioned above also occurs in the fdiv instruction.
Example:
When executing the instruction fdiv.d fs9, fs10, fa4 with the following register values:
fs10 = 0x41ddc16575c00000
fa4 = 0x41e0000c09000000
The results differ between CVA6 and Spike simulator as follows:
Round Toward Zero (RTZ) Mode:
CVA6 Result: 0x3fedc14f1407f47f
Spike Result: 0x3fedc14f1407f47e (correct value as verified)
Round Up (RUP), Round to Nearest, Tie to Max Magnitude (RMM), and Dynamic (DYN) Rounding Modes:
CVA6 Result: 0x3fedc14f1407f47e
Spike Result: 0x3fedc14f1407f47f
from cva6.
JeanRochCoulon
commented on June 18, 2024
This Github issue can also be reported on cvfpu side, thanks
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Related Issues (20)
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- ZCB RISCV compilor in smoke-gen_tests HOT 5
- Parametrization: dependencies with HPDCache HOT 4
- DRAM and AXI interconnect throughput with single-beat master HOT 1
- How to flush the data cache? HOT 2
- [BUG] Hardcoded 300s Timeout Issue during VCS Compile/RTL Simulation in cva6.py HOT 5
- what the flag of the RV_test pass or failed with spike HOT 2
- [BUG] riscv-arch-tests no longer executed in CI HOT 1
- [BUG] Allowing illegal access to addresses outside the PMP range and memory boundaries. HOT 6
- [BUG] External supervisor mode interrupt HOT 1
- [BUG] Incorrect Accumulation of ‘OF’ Flag in fflags After Executing fsqrt.d on Infinity HOT 1
- [BUG] Incorrect Result from 'fdiv' Operation Leading to Negative Infinity Instead of Smallest Negative Number HOT 2
- [BUG] Incorrect Setting of DZ Flag for 0/0 Division HOT 1
- [BUG] Failure to Trigger NX Exception Under Specific Microarchitectural Conditions
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- Purpose of AXI_BUS, axi_master_connect dependency with axi_switch_vif in uvm_testbench HOT 8
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