Generate hex file

[openhwgroup]

Generate hex file

[zarubaf]

The elf2hex command is absolutely correct. The reason why you run out of memory is that Questasim is not using riscv-fesvr which handles the communication with the target. It just implements the the end-of-computation signal coming from the DUT (store to .tohost address with LSB set). This works fine with the basic riscv-tests but fails on the benchmarking suit as all benchmarks want to write to stdout. The benchmark is waiting for an acknowledgement of the host which it is basically never getting.

That beeing said, I am unsure whether I will implement the missing functionality because the way host-target communication is currently handled within riscv-fesvr and riscv-tests is quite messy with non-cache coherent systems. The Verilator testbench handles this simulation though and should let you do the benchmarking.

[hoangt]

Thanks for explanations. I might need to look at Verilator and mimic (hopefully) for Questasim. Is there any plan to build a SoC based on this core and support FPGA prototype!

[zarubaf]

Would be happy to accept a PR with this added functionality. Yes, indeed - we do have a SoC based on this core which also supports FPGA mapping. It is still in somehow a messy state but will be pushed quite soon.