Comments (5)
That's amazing, thanks @HamzaShabbir517
The OpenHW Group team is already working in fixing the divider, but this document will definitively be very useful for them
@lucabertaccini @MikeOpenHWGroup @pascalgouedo @JeanRochCoulon @jquevremont
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Thanks for this @HamzaShabbir517! As @davideschiavone indicated, the OpenHW Group has started a complete verification cycle of the CV32E40Pv2+CVFPU. This effort is being led by @pascalgouedo. In addition @lucabertaccini will be updating the DIV logic in the CVFPU.
This work has just begun, and we have encountered multiple issues (which will be captured as issues in this repository very soon). Your input will be very useful to this effort. As we get closer to completion of this verification effort, may we ask you to re-run your tests again?
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@davideschiavone thanks for the quick response.
@MikeOpenHWGroup Sure please let me know when the errors are resolved as we have developed a Verification Environment in which we can generate Random Floating Point Numbers and we can also give millions of inputs to the design and compare the result against the ISS.
A glimpse of number of random inputs generated for some instructions is shown below.
Regards:
Hamza Shabbir
Research Associate
MERL
from cvfpu.
Hi there,
Since FNMADD
and FNMSUB
both produce false results with an inverted sign bit in your screenshots, can it be that the two ops are swapped in their encoding?
Cheers
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@stmach Yes that's the issue the opcodes have been swapped
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Related Issues (20)
- C/C++ example for float16alt
- Is it possible to do BF16*int8 + int8 using this IP ?
- Is it possible to do BF16*int8 + int8 using this IP ? #103
- how complicated would it be add FP8 E3M4 and E2M5 support to this IP? HOT 2
- DC Synthesis for cvfpu (fpnew) occurs fatal error HOT 4
- [Bug] Incorrect Accumulation of ‘OF’ Flag in fflags After Executing fsqrt.d on Infinity HOT 1
- [BUG] Incorrect Result from 'fdiv' Operation Leading to Negative Infinity Instead of Smallest Negative Number
- [BUG] Incorrect Accumulation of ‘OF’ Flag in fflags After Executing fsqrt.d on Infinity
- [BUG] Unexpected Rounding Behavior During fsqrt.d Execution
- Proposal: allow the FMA addend to be in either `src_fmt_i` or `dst_fmt_i` HOT 5
- NONCOMP clears the result bit for signaling NaNs in "not equal" compare HOT 1
- SQRT operation for FP16ALT only works when all op[n] lanes are assigned to the same input
- Unexpected Result When fsqrt.s Processes Negative Floating-Point Numbers HOT 4
- fdiv incorrectly returns infinity when dividing by NaN HOT 3
- [BUG] Incorrect fflags Set When Using fdiv Instruction to Divide by Infinity
- Conversion from FP32 -2^31 to INT32 sets NV status HOT 5
- Bug report: FSQRT of non-canonical NaN gives valid large floats
- Bug report: fdiv.s taking two NaN may return a valid number and is not always the consequence of a wrong rounding
- Bug report: multifmt slice uses wrong FP width for third operand HOT 3
- Underflow flag not set at subnormal/normal boundary HOT 13
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