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davideschiavone avatar davideschiavone commented on August 17, 2024

That's amazing, thanks @HamzaShabbir517

The OpenHW Group team is already working in fixing the divider, but this document will definitively be very useful for them

@lucabertaccini @MikeOpenHWGroup @pascalgouedo @JeanRochCoulon @jquevremont

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MikeOpenHWGroup avatar MikeOpenHWGroup commented on August 17, 2024

Thanks for this @HamzaShabbir517! As @davideschiavone indicated, the OpenHW Group has started a complete verification cycle of the CV32E40Pv2+CVFPU. This effort is being led by @pascalgouedo. In addition @lucabertaccini will be updating the DIV logic in the CVFPU.

This work has just begun, and we have encountered multiple issues (which will be captured as issues in this repository very soon). Your input will be very useful to this effort. As we get closer to completion of this verification effort, may we ask you to re-run your tests again?

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HamzaShabbir517 avatar HamzaShabbir517 commented on August 17, 2024

@davideschiavone thanks for the quick response.
@MikeOpenHWGroup Sure please let me know when the errors are resolved as we have developed a Verification Environment in which we can generate Random Floating Point Numbers and we can also give millions of inputs to the design and compare the result against the ISS.
A glimpse of number of random inputs generated for some instructions is shown below.

Screenshot from 2022-09-02 22-13-46

Regards:
Hamza Shabbir
Research Associate
MERL

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stmach avatar stmach commented on August 17, 2024

Hi there,

Since FNMADD and FNMSUB both produce false results with an inverted sign bit in your screenshots, can it be that the two ops are swapped in their encoding?

Cheers

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HamzaShabbir517 avatar HamzaShabbir517 commented on August 17, 2024

@stmach Yes that's the issue the opcodes have been swapped

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