opentimer/parser-verilog

A Standalone Structural Verilog Parser

parser-verilog's Issues

Compile Issues

Thanks for really great work!
I've found two compile issues regarding with this Verilog parser.

1. Flex 2.5.37 is compile-able, but flex 2.6.4 generated compile error.
   Below command,

    $ flex -o ./verilog_lexer.yy.cc parser-verilog/verilog_lexer.l 
   

   the verilog_lexer.yy.cc from Flex 2.5.37 is working for me, but the verilog_lexer.yy.cc from Flex 2.6.4 generated compile error.
   I've attached compiled verilog_lexer_yy.cc file just in case.
   ( Compile environment: Centos 7 / GCC 8.2.0 )
   verilog_lexer.zip

2. The below command was working in my environments.

    $ g++ -std=c++17 -I./ -Iparser-verilog/ verilog_parser.tab.cc verilog_lexer.yy.cc example/sample_parser.cpp -o sample_parser -lstdc++fs
   

Got syntax error on using '&' or '~'

module and_gate (
input a,
input b,
output out
);
assign out = a & b;

endmodule

Build error

Hi,
I am trying to build Parser-Verilog on my ubuntu system. I am getting the following error from make command.

/usr/bin/cmake -H/home/<...>/Parser-Verilog -B/home/<...>/Parser-Verilog/build --check-build-system CMakeFiles/Makefile.cmake 0
/usr/bin/cmake -E cmake_progress_start /home/<...>/Parser-Verilog/build/CMakeFiles /home/<...>/Parser-Verilog/build/CMakeFiles/progress.marks
make -f CMakeFiles/Makefile2 all
make[1]: Entering directory '/home/<...>/Parser-Verilog/build'
make -f CMakeFiles/regression.dir/build.make CMakeFiles/regression.dir/depend
make[2]: Entering directory '/home/<...>/Parser-Verilog/build'
[  5%] [FLEX][verilog_lexer] Building scanner with flex 2.6.4
cd /home/<...>/Parser-Verilog && /usr/bin/flex -o/home/<...>/Parser-Verilog/build/verilog_lexer.yy.cc /home/<...>/Parser-Verilog/parser-verilog/verilog_lexer.l
[ 11%] [BISON][verilog_parser] Building parser with bison 3.0.4
cd /home/<...>/Parser-Verilog && /usr/bin/bison -d -o /home/<...>/Parser-Verilog/build/verilog_parser.tab.cc /home/<...>/Parser-Verilog/parser-verilog/verilog_parser.yy
/home/<...>/Parser-Verilog/parser-verilog/verilog_parser.yy: warning: 2 shift/reduce conflicts [-Wconflicts-sr]
/home/<...>/Parser-Verilog/parser-verilog/verilog_parser.yy:6.9-24: error: %define variable 'api.parser.class' is not used
 %define api.parser.class {VerilogParser}
         ^^^^^^^^^^^^^^^^
CMakeFiles/regression.dir/build.make:64: recipe for target 'verilog_parser.tab.cc' failed
make[2]: *** [verilog_parser.tab.cc] Error 1
make[2]: Leaving directory '/home/<...>/Parser-Verilog/build'
CMakeFiles/Makefile2:70: recipe for target 'CMakeFiles/regression.dir/all' failed
make[1]: *** [CMakeFiles/regression.dir/all] Error 2
make[1]: Leaving directory '/home/<...>/Parser-Verilog/build'
Makefile:97: recipe for target 'all' failed
make: *** [all] Error 2

Also attaching CMake log -

-- The CXX compiler identification is GNU 7.5.0
-- Check for working CXX compiler: /usr/bin/c++
-- Check for working CXX compiler: /usr/bin/c++ -- works
-- Detecting CXX compiler ABI info
-- Detecting CXX compiler ABI info - done
-- Detecting CXX compile features
-- Detecting CXX compile features - done
-- Found BISON: /usr/bin/bison (found version "3.0.4") 
-- Found FLEX: /usr/bin/flex (found version "2.6.4") 
-- Configuring done
-- Generating done
-- Build files have been written to: /home/<...>/Parser-Verilog/build

Has anyone else encountered this error before ?

Parse issues with delimiter.

I've found out that below wire definition with delimiter generated below problem.
Could you fix this issue?

For example, below two wire definition generated below logs.

wire \fifo_in/enq_i;
wire \fifo_in/tail_r;

These generated below error.

Failed to match : \
Parser error: syntax error, unexpected end of file, expecting ';' or ','
  begin at line 68 col 16
  end   at line 68 col 17
Aborted (core dumped)

OpenSTA's verilog parser could handle this, but ben-marshall's parser is not able to handle this...

Do parser-verilog support behavorial-level RTL code?

It seems that the parse only support netlist level verilog code? Does it support behavorial level verilog?
For example, the reg key word seems not supported yet?

Publish to conan

Hi,

Would it be possible to publish the code to conan ?
I have tried modifying it to be publishable, but my conan-fu is miserable ...

escaped name that ends at end of line fails

If I have this structure, where the escaped name is the last item on the line.
wire \n_12 , \n_13
, \n_14 , \n_15 ;

I will get:
Failed to match :
Parser error: syntax error, unexpected end of file, expecting NAME or ESCAPED_NAME

The synthesis programs I use sometimes create the above structure.

If the line had the comma at the end, then it reads ok.
wire \n_12 , \n_13 ,
\n_14 , \n_15 ;

Out Of Tree Build Fails

Hi there,

I have cloned your repository, and found that the sequence of commands:

git clone https://github.com/OpenTimer/Parser-Verilog.git
cd Parser-Verilog
mkdir build
cd build
cmake ../
make

Fails to build.

It would appear that include path is not correct:

/home/mypath/Parser-Verilog/parser-verilog/verilog_scanner.hpp:8:10: fatal error: verilog_parser.tab.hh: No such file or directory
 #include "verilog_parser.tab.hh"

However, building in tree works fine.

My platform is Ubuntu 18.04.