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chiptools's Introduction

ChipTools is a utility to automate FPGA build and verification

Documentation Status Build Status

What can it do?

ChipTools aims to simplify the process of building and testing FPGA designs by providing a consistent interface to vendor applications and automating simulation and synthesis flows.

Key features

  • Seamlessly switch between vendor applications without modifying build scripts or project files.
  • Enhance testbenches with Python based stimulus generation and checking.
  • Automate test execution and reporting using the Python Unittest framework.
  • Automatically check and archive build outputs.
  • Preprocess and update files before synthesis to automate tasks such as updating version registers.
  • Free and open source under the Apache 2.0 License.

Getting Started

  # Clone the ChipTools repository to your system:
  $ git clone --recursive https://github.com/pabennett/chiptools.git
  
  # Install using the setup.py script provided in the root directory:
  $ cd chiptools
  $ python setup.py install
  
  # Start the ChipTools command line interface:
  $ cd examples/max_hold
  $ chiptools
  
  # Load the example project:
  (cmd) load_project max_hold.xml
  
  # Run the testsuite using Modelsim:
  (cmd) run_tests modelsim
  
  # ...or Vivado (GHDL and ISIM are also supported):
  (cmd) run_tests vivado
  
  # Synthesise the max_hold component in the lib_max_hold library (ISE, Vivado and Quartus are supported)
  (cmd) synthesise lib_max_hold.max_hold

Refer to the documentation for examples on using ChipTools to simulate and build FPGA designs.

Supported Tools

The following tools are currently supported, support for additional tools will be added in the future.

Simulation Tools

  • Modelsim (tested with 10.3)
  • ISIM (tested with 14.7)
  • GHDL (tested with 0.31)
  • Vivado (tested with 2015.4)
  • Icarus (tested with 0.9.7)

Synthesis Tools

  • Xilinx ISE (tested with 14.7)
  • Quartus (tested with 13.1)
  • Vivado (tested with 2015.4)

chiptools's People

Contributors

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chiptools's Issues

Vivado simulator wrapper generic assignment

The Vivado simulator wrapper is unable to set top-level generics during simulation because the command line switch "-generic_top" does not work as documented in UG900 (p89)

According to the documentation, xelab accepts a command line argument of the form -generic_top "P1=10" in order to set a top level generic during elaboration, however doing so results in the following error:

xelab -generic_top "data_width=32" lib_tb_max_hold.tb_max_hold
ERROR: [XSIM 43-3225] Cannot find design unit work.'32' in library work located at xsim.dir/work.

If spaces are inserted between the '=' and the name+value the command is recognised correctly, but the spaces prevent the name+value from being correctly set:

xelab -generic_top "data_width =32" lib_tb_max_hold.tb_max_hold
ERROR: [XSIM 43-3281] Parameter/Generic data_width   specified in commandline not found in design.

xelab -generic_top "data_width= 32" lib_tb_max_hold.tb_max_hold
ERROR: [VRFC 10-1509] unknown actual generic literal value  32 for generic data_width ignored

xelab -generic_top "data_width = 32" lib_tb_max_hold.tb_max_hold
ERROR: [XSIM 43-3281] Parameter/Generic data_width   specified in commandline not found in design.

If the name+value and '=' are encapsulated in double quotes the command will work, e.g:

xelab -generic_top "data_width""=""32" lib_tb_max_hold.tb_max_hold

However, this may not work on all platforms (this was tested on Windows) and the underlying subprocess.Popen routine does not seem to be able to pass an argument using this unconventional form.

Error installing

What is this error?

$ python setup.py install
Traceback (most recent call last):
  File "setup.py", line 5, in <module>
    from setuptools import find_packages, setup, Command
ImportError: No module named setuptools

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