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Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. UART, I2C protocols.

Pascal 0.24% JavaScript 13.67% Shell 4.20% Batchfile 2.38% Tcl 15.13% HTML 29.64% Verilog 20.45% C 14.28% PureBasic 0.01%
mips-processor soc fpga-validation performance-analysis truth-tables uart-verilog

computer-architecture-design's Introduction

Hello World! I'm Phat 👋

GIF

I'm a recently Graduate, Developer, Creator, and Mentor!!

  • 🔭 I’m currently working as Software Quality Assurance Engineer at Neato Robotics
  • 🪴 I'm recently graduated as Bachelor in Computer Engineer at San Jose State University Anti Car Theft Camera System
  • 👯 I’m looking to collaborate on open source
  • 🤔 I’m actively looking for a full-time job in the robotics/software/hardware engineering career
  • 💬 Ask me about ANYTHING
  • 😄 Pronouns: He/Him
  • ⚡ Fun fact: I speak 2 languages(Vietnamese, English), play instruments(guitar🎸, piano🎹), and a father of 10 succulents🪴, and 5 cacti🌵

Talk with me, I am kinda awesome:

PhatLe | LinkedIn


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Visual Studio Code JIRA JavaScript React

CSharp

python

GitHub

Terminal

Terminal



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