Comments (5)
Task 1 finished in #29
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I imagine the Python interface to look something like
ctx = Context()
stdlib = ctx.load_library("stdlib")
To do this, it could dispatch on the argument to load_library
and call the correct function coreir_stdlib.CoreIRLoadLibrary_stdlib(ctx)
but either:
- The coreir library (e.g. stdlib) defines an
extern C
function and uses thecoreir-c
opaque types, or - The library registers itself with the C-api which holds a map between strings to library function pointers and provides a C-api function
coreir_lib.LoadLibrary(ctx, name)
which handles converting theNamespace*
andContext*
between cpp and opaque types.
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@leonardt In regards to #2, how does the library register itself with the C-api? I think it would still necessarily involve writing an extern C function per library. Unless I am misunderstanding something...
That being said, it would be cool to be able to register library functions which would mean no need for a specific function name standard.
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@leonardt I just pushed to the clibfix branch (off of libreorg) the addition of the C stdlib api. There are three TODOs (one in lib/libs/stdlib.cpp, two in include/coreir-libs/stdlib.h)
It would be awesome if you could make macros (defined in include/coreir.h) that would macrofy each of the 3 TODOs.
Also now that we have the C api for the libs, you can add them to the python bindings
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README updated -- link
@rdaly525 Should I submit a PR for this branch or are there other fixes pending? I'll wait to close this issue until we merge the branch.
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Related Issues (20)
- Add module longname C API
- Compilation error on Apple M1 chip HOT 11
- Request for CoreIR compatible with Windows. HOT 1
- InstanceVisitorPass does not allow passing in functors that have access to the class object itself.
- Need to change googletest tag from master to main HOT 2
- google test throws sign conversion warnings
- Add a Custom Name for CoreIR Generator When Generate Verilog HOT 14
- Cannot get two bit types to wire together regardless of direction? HOT 3
- [RFC] Bit Pattern Support in coreir HOT 6
- Regression in inline commonlib mux verilog generation
- Verilog backend can clobber names when generating instance output port wires
- Having trouble at branch rm-ubuf-master HOT 3
- inline_single_instance pass should maintain instance name HOT 1
- Update JSON for Modern C++
- Why is IEEE compliance for CW floating point add/mul set to 0? HOT 2
- verilog ND-array generation should be packed arrays instead of unpacked arrays. HOT 3
- Add Multiply optimization
- segfault when using prototype components. HOT 44
- [feature request] adding prefix to coreir/commonlib/... verilog modules HOT 4
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