ria-jit/ria-jit

Lightweight and performant dynamic binary translation for RISC–V code on x86–64

Dynamic Binary Translation (RISC-V -> x86) 🛠

Make RISC-V code executable on the x86-64 ISA by means of dynamic binary translation.

🏠 Homepage

Paper

You can find the source code of the paper under documentation. It is also published at researchgate.net.

Building the translator

After checking out the git repository (and running git submodule update --init to fetch the dependencies), the translator can be built via

1. sudo apt-get -y install gcc g++ cmake make autoconf meson (required dependencies)
2. mkdir build && cd build && cmake .. && make

We can execute binaries compiled via the RISC-V toolchain gcc and the options -static -march=rv64imafd -mabi=lp64d.

Usage

Usage: ./translator [translator option(s)] -f <filename> [guest options]

Options:
	-v, --version
		Show translator version.
	-f, --file <executable>
		Specify executable. All options after the file path are passed to the guest.
	-a, --analyze-all
	--analyze-mnem, --analyze-reg, --analyze-pattern
		Analyze the binary. Does not execute the guest program.
		Inspects passed program binary and shows the selected statistics.
	-b, --benchmark
		Benchmark execution. Times the execution of the program,
		excluding mapping the binary into memory.
	-p, --profile
		Profile register usage. Display dynamic register usage statistics.
	--perf
		Log the generated blocks to /tmp/perf-<pid>.map for externally profiling
		the execution in perf.
	-s, --fail-silently
		Fail silently for some error conditions.
		Allows continued execution, but the client program may enter undefined states.
	-h, --help
		Show this help.

Logging:
	--log=category,[...]
		Enable logging for certain categories. See --log=help for more info.
	-g	Display general verbose info (--log=general,strace)
	-i	Display parsed RISC-V input assembly (--log=asm_in)
	-o	Display translated output x86 assembly (--log=asm_out,verbose_disasm)
	-r	Dump registers on basic block boundaries (--log=reg)
	-c	Display cache info (--log=cache)

Optimization:
	--optimize=category,[...]
		Disable certain optimization categories. See --optimize=help for more info.
	-d	Enable Single stepping mode.
		Each instruction will be its own block. (--optimize=singlestep)
	-m	Disable all translation optimization features. (--optimize=none)

Run tests

./test

Authors

👤 Noah Dormann, Simon Kammermeier, Johannes Pfannschmidt, Florian Schmidt

• GitHub: @Artemis-Skade, @Simon04090, @johaza, @flodt

Supervisor

👤 Alexis Engelke

• TUM: Alexis Engelke, M. Sc.
• GitHub: @aengelke

ria-jit's Issues

RISC-V compliance test

Hi,

I am curious whether this DBT is capable passing riscv-compliance test in this repo or whether you are interested in implementing this feature in the near future ?

BTW your work is amazing, implementing a DBT that out performs qemu is exceptional. Thanks you all for making it open source.